14 posts tagged with "NVIDIA"

June 2026 saw multiple milestone events in the AI chip field, marking acceleration of two major trends: "domestic substitution" and "de-NVIDIA-ization."

1. Huawei Ascend 910C Completes 1.6-Trillion-Parameter DeepSeek V4 Pro Training (2026-06-05)​

Event Overview​

June 5, 2026, Shenzhen Hetao College, together with Harbin Institute of Technology (Shenzhen), Shenzhen Big Data Research Institute, Huawei, and other teams, relied on an Ascend 910C domestic AI compute cluster to successfully complete full-parameter post-training of the 1.6-trillion-parameter DeepSeek V4 Pro large model.

Technical Significance​

Metric	Value
Model parameters	1.6 trillion
Training chip	Ascend 910C cluster
Training type	Full Parameter Post-Training
Significance	First time domestic AI chips complete trillion-parameter-level model training

Industry Impact​

1. Breaks technology blockade: Proves domestic AI chips can train trillion-parameter models
2. Accelerates "farewell to NVIDIA": DeepSeek fully switches to Huawei Ascend, reducing dependence on H100
3. Domestic substitution inflection point: From "inference substitution" to "training substitution"

Related Links​

• Huawei Ascend 910C spec page
• DeepSeek V4 Pro official announcement (pending)

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2. OpenAI Launches First Custom AI Inference Chip Jalapeño (2026-06-24)​

Event Overview​

June 24, 2026, OpenAI and Broadcom jointly launched the first custom AI inference chip Jalapeño, with a design cycle of only 9 months (industry average 18 months), using TSMC 3nm process.

Key Metrics​

Metric	Jalapeño	Comparison (Blackwell)
Process	TSMC 3nm	TSMC 4nm
Architecture	Systolic Array	Blackwell GPU
Design cycle	9 months	~18 months
Inference cost	-50%	Baseline
AI-assisted design	✅ First	❌ No
Deployment	End of 2026	Shipped

Strategic Significance​

1. First AI chip with AI-assisted design: OpenAI used models like GPT-5.3-Codex-Spark to assist architecture exploration
2. Accelerates "de-NVIDIA-ization": Tech giants (Google, Amazon, Microsoft, Meta, OpenAI) collectively develop custom chips
3. Inference cost revolution: For OpenAI processing hundreds of millions of API calls daily, a 50% cost reduction is significant

Related Links​

• OpenAI Jalapeño spec page
• OpenAI Custom Chip Deep Dive

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3. NVIDIA Launches RTX Spark AI PC Superchip at Computex 2026 (2026-06-01)​

Event Overview​

June 1, 2026, NVIDIA CEO Jensen Huang launched the RTX Spark AI PC superchip at Computex 2026 / GTC Taipei, in collaboration with MediaTek, using an Arm CPU + Blackwell GPU unified-memory architecture.

Key Metrics​

Metric	RTX Spark
CPU	Up to 20-core Arm (with MediaTek)
GPU	6,144 CUDA cores (Blackwell)
Unified memory	128GB LPDDR5X (shared CPU+GPU)
Memory bandwidth	300 GB/s
AI compute	~1 PFLOPS (est.)
Model capacity	Can run 120B-parameter models
Context	Up to 1 million tokens
TDP	~100W (est.)
Availability	Fall 2026

Industry Impact​

1. NVIDIA enters PC chip market: Challenges Intel's dominance in personal computers
2. New AI PC standard: Run 120B-parameter models locally, 1M-token context
3. Windows transforms into AI Agent platform: Deep collaboration with Microsoft OpenShell framework

Related Links​

• NVIDIA RTX Spark spec page
• Computex 2026 Chip War Deep Dive (external link)

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4. MIIT Publishes "2026 AI Chip Industry Development White Paper" (2026-06-09)​

Event Overview​

June 9, 2026, China's Ministry of Industry and Information Technology published the "2026 AI Chip Industry Development White Paper," predicting the domestic AI chip market will exceed 200 billion RMB in 2026.

Key Predictions​

Metric	2026 Prediction
Market size	Exceed 200 billion RMB
Domestic chip share	>50% (41% in 2025)
Edge inference chips	Significant progress
Shipment growth	More than double (vs 2025)

Industry Significance​

1. Domestic AI chip capitalization accelerates: Cambricon, Enflame, Moore Threads, etc. accelerate IPOs
2. Edge inference becomes the breakthrough: Easier to achieve domestic substitution than training chips
3. Policy dividend continues: Domestic substitution upgraded from "market behavior" to "national strategy"

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5. ByteDance in Talks to Procure 50K Iluvatar Inference Chips (2026-06-17)​

Event Overview​

June 17, 2026, Reuters reported that ByteDance is in talks with Shanghai AI chip firm Iluvatar to procure at least 50,000 AI chips, mainly for inference tasks.

Deal Details​

Item	Content
Buyer	ByteDance
Supplier	Iluvatar
Chip model	ZhiKai series (inference GPU)
Quantity	At least 50,000
Use	Inference workloads
Training chip	TianTai series

Industry Significance​

1. Domestic GPU top player "adds a member": Iluvatar enters a top internet company's supply chain for the first time
2. ByteDance 2026 capex raised over 200B RMB: Mainly for AI compute and datacenters
3. "Domestic substitution" extends from government/SOEs to private tech giants

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Summary: Three Trends in June 2026 AI Chip Industry​

Trend 1: "Domestic Substitution" Moves from Inference to Training​

• Ascend 910C completes 1.6-trillion-parameter model training → Proves domestic chips have training capability
• DeepSeek fully switches to Ascend → Leading AI companies first to "farewell to NVIDIA"
• ByteDance procures Iluvatar → Private tech giants follow

Trend 2: "De-NVIDIA-ization" from Slogan to Action​

• OpenAI Jalapeño → First custom chip, inference cost -50%
• Google TPU, Amazon Trainium, Microsoft Maia → Continuous iteration
• Meta MTIA, Apple M5 Ultra → Increased investment

Trend 3: AI PC and Edge Inference Become New Battlefield​

• NVIDIA RTX Spark → New AI PC standard, launches Fall 2026
• Edge inference chip localization accelerates → Key mention in MIIT white paper
• "Local trillion-parameter model execution" → New consumer market selling point

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Looking Ahead (2026 H2)​

1. Ascend 950DT full scale-up (2026 Q4) → Huawei's latest-gen training chip
2. NVIDIA Rubin R200 shipment (2026 H2) → Next-gen flagship
3. AMD MI400 Helios rack (2026 H2) → Targets NVIDIA GB200
4. OpenAI Jalapeño deployment (end of 2026) → Gigawatt-scale datacenters
5. Domestic AI chip shipments more than double → CITIC Securities prediction

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References​

• Huawei Ascend 910C Completes DeepSeek V4 Pro Training - Tencent News
• OpenAI Jalapeño Chip Launch - CNBC
• NVIDIA RTX Spark Launch - Tencent News
• MIIT AI Chip White Paper - RayByte
• ByteDance Procures Iluvatar Chips - Sina Finance

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This article is continuously updated. Please provide the latest developments.

In 2026, against the backdrop of U.S. export controls on AI chips to China, Cambricon's MLU690 has drawn intense attention as a "China-made H100." This article compares the two in depth across compute, memory, power, software ecosystem, measured performance, and price to help you make a selection decision.

Core Verdict (Read This First)​

Dimension	MLU690	H100	Winner	Gap
BF16 compute	600 TFLOPS	989 TFLOPS	H100	+65%
Memory capacity	64GB HBM3	80GB HBM3	H100	+25%
Memory bandwidth	2 TB/s	3.35 TB/s	H100	+68%
TDP	280W	700W	MLU690	-60%
Energy efficiency	2.14 TFLOPS/W	1.41 TFLOPS/W	MLU690	+52%
Software ecosystem	NeuWare (~75% coverage)	CUDA (100% coverage)	H100	large gap
Price	~¥140,000	~¥200,000	MLU690	-30%
Availability	domestic spot stock	export-controlled	MLU690	✅

One-line summary: MLU690 delivers roughly 60% of H100's compute, but at only 40% of the power and 70% of the price — a strong fit for AI training and inference in the Chinese market.

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1. Detailed Spec Comparison​

1.1 Compute​

Precision	MLU690	H100 SXM5	H200 SXM5	Note
FP8	~300 TFLOPS (est.)	3,958 TFLOPS	3,958 TFLOPS	H100 supports FP8; MLU690 likely does not
BF16/FP16	600 TFLOPS	989 TFLOPS	989 TFLOPS	H100 leads by 65%
FP32	~150 TFLOPS (est.)	60 TFLOPS	60 TFLOPS	MLU690 estimate; H100 actually higher
INT8	1,200 TOPS	1,979 TOPS	1,979 TOPS	H100 leads by 65%

Key findings:

• ✅ MLU690 reaches 60% of H100's BF16 compute
• ⚠️ H100 supports FP8 (4-bit); MLU690 likely does not (needs confirmation)
• ⚠️ H100's higher INT8 compute favors inference scenarios

1.2 Memory​

Item	MLU690	H100	H200	Note
Capacity	64GB HBM3	80GB HBM3	141GB HBM3e	H200 largest
Bandwidth	2 TB/s	3.35 TB/s	4.8 TB/s	H200 highest
Type	HBM3	HBM3	HBM3e	H200 uses latest HBM3e

Key findings:

• ⚠️ MLU690 has 20% less memory than H100 (64GB vs 80GB)
• ⚠️ MLU690 bandwidth is 40% lower than H100 (2 TB/s vs 3.35 TB/s)
• ❌ When running 70B+ parameter models, MLU690 may run out of memory (model parallelism required)

1.3 Power​

Item	MLU690	H100	H200
TDP	280W	700W	700W
Efficiency (FP16/W)	2.14 TFLOPS/W	1.41 TFLOPS/W	1.41 TFLOPS/W
8-card server power	~3.5kW	~6kW	~6kW
Annual electricity (¥0.6/kWh)	~¥18,400	~¥36,800	~¥36,800

Key findings:

• ✅ MLU690 draws only 40% of H100's power, sharply cutting data-center electricity cost
• ✅ MLU690 leads efficiency by 52%, better suited to large-scale deployment
• ✅ For power-sensitive inference, MLU690 has a clear edge

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2. Software Ecosystem​

2.1 Framework Support​

Framework	MLU690 (NeuWare)	H100 (CUDA)	Note
PyTorch	✅ (PyTorch-Cambricon)	✅ native	MLU690 needs an extra plugin
TensorFlow	✅ (TensorFlow-Cambricon)	✅ native	same
JAX	⚠️ partial	✅ native	MLU690 limited
ONNX	⚠️ partial	✅ native	same
vLLM	⚠️ in progress	✅ native	MLU690 awaits community port

2.2 Operator Coverage​

Category	MLU690	H100	Note
Basic operators	✅ 95%	✅ 100%	conv, matmul, etc.
Transformer operators	✅ 85%	✅ 100%	Attention, LayerNorm, etc.
Custom operators	⚠️ hand-written	✅ CUDA C++	MLU690 harder to develop
LLM inference opt.	⚠️ basic	✅ mature (FlashAttention, PagedAttention)	H100 leads

Key findings:

• ⚠️ NeuWare is only 5–6 years old, with ~75–85% operator coverage
• ❌ Complex LLMs (e.g., GPT-4, Claude) may need manual optimization
• ✅ Common models (Llama, Qwen, GLM) are essentially already supported

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3. Measured Performance​

3.1 Training​

Model	MLU690 (time)	H100 (time)	Speedup
Llama 7B	~48 h (est.)	~30 h	1.6x
Llama 70B	~7 days (est.)	~4.5 days	1.6x
Qwen 72B	~8 days (est.)	~5 days	1.6x

Note: above figures are estimates; real performance depends on software optimization.

3.2 Inference​

Model	MLU690 (tok/s)	H100 (tok/s)	Note
Llama 7B	~80 tok/s (est.)	~120 tok/s	H100 +50%
Llama 70B	~20 tok/s (est.)	~35 tok/s	H100 +75%
Qwen 72B	~18 tok/s (est.)	~30 tok/s	H100 +67%

Key findings:

• ⚠️ H100 leads inference by 50–75%
• ✅ But MLU690 draws only 40% the power, with better efficiency
• ✅ For cost-sensitive inference, MLU690 is more economical

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4. Price​

4.1 Hardware Procurement​

Item	MLU690	H100	H200
Per-card (domestic)	~¥140,000	~¥200,000	~¥300,000
8-card server (turnkey)	~¥1,200,000	~¥1,800,000	~¥2,600,000
Cost gap	-	+50%	+117%

4.2 TCO (3 years)​

Item	MLU690	H100	Note
Hardware	¥1,200,000	¥1,800,000	MLU690 33% cheaper
Electricity (3y)	¥55,200	¥110,400	MLU690 50% cheaper
Facility	¥150,000	¥250,000	MLU690 40% cheaper
TCO (3y)	¥1,405,200	¥2,160,400	MLU690 35% cheaper

Key findings:

• ✅ MLU690's TCO is 35% lower than H100's
• ✅ For large-scale deployment (100+ cards), the cost advantage is pronounced

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5. Selection Advice​

5.1 Choose MLU690 if...​

• ✅ Your business is primarily in the Chinese market
• ✅ You are affected by U.S. export controls and cannot buy H100/H200
• ✅ You are power-sensitive (edge data centers, high electricity-cost regions)
• ✅ Your models use common architectures (Llama, Qwen, GLM)
• ✅ You have domestic-substitution requirements (government, SOEs, military)

5.2 Choose H100/H200 if...​

• ✅ Your business is global
• ✅ You need to train frontier models (GPT-4 class)
• ✅ Your models use complex operators (need the CUDA ecosystem)
• ✅ You demand extreme performance (low-latency inference)
• ✅ You can legally procure H100/H200

5.3 Hybrid deployment (recommended)​

Scenario	Recommended
Training	H100 (high perf) + MLU690 (low-cost scale-out)
Inference	MLU690 (cost-sensitive) + H100 (low-latency)
Domestic project	all MLU690
International market	all H100/H200

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6. Outlook​

6.1 MLU690's weaknesses​

• ⚠️ Immature software ecosystem: 75–85% operator coverage; complex models need manual tuning
• ⚠️ Small memory: 64GB limits support for 70B+ parameter models
• ⚠️ Weak interconnect: Cambricon Link bandwidth below NVLink
• ⚠️ Limited international market: affected by U.S. export controls

6.2 MLU690's improvement path​

• 📅 MLU790 (2027): expected 5nm process, ~2x compute
• 📅 Memory upgrade: next gen may adopt HBM3e, capacity up to 128GB
• 📅 Software: NeuWare ecosystem improving, operator coverage target 95%

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7. Summary​

Dimension	MLU690	H100	Recommended scenario
Compute	⭐⭐⭐⭐	⭐⭐⭐⭐⭐	H100 for top-tier training
Memory	⭐⭐⭐	⭐⭐⭐⭐	H100 for large models
Power	⭐⭐⭐⭐⭐	⭐⭐⭐	MLU690 for inference
Ecosystem	⭐⭐⭐	⭐⭐⭐⭐⭐	H100 for complex models
Price	⭐⭐⭐⭐⭐	⭐⭐⭐	MLU690 for large-scale deployment
Domestic	⭐⭐⭐⭐⭐	❌	MLU690 for Chinese market

Final recommendation:

• 🇨🇳 Chinese market: prefer MLU690 (domestic + low cost)
• 🌍 International market: prefer H100/H200 (performance + ecosystem)
• 💡 Hybrid: train on H100, infer on MLU690

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References​

• Cambricon MLU690 spec page
• NVIDIA H100 spec page
• Full AI chip comparison table
• TCO calculator

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Disclaimer: Data in this article is based on public sources and reasonable estimates; actual performance is subject to vendor official testing. MLU690's software ecosystem is evolving rapidly — watch NeuWare updates.

Last updated: 2026-06-23

June 2026 update — the AI compute card market is undergoing its most dramatic reshuffling in years. This article walks through the latest roadmap developments.

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Key Takeaways​

• Qualcomm AI 200/250 officially enters the datacenter AI inference market, targeting NVIDIA H200
• AMD MI400 series unveils three models: MI430X (HPC), MI440X (enterprise), MI455X (flagship)
• Huawei publishes a three-generation roadmap: 950 (2026) → 960 (2027-Q4) → 970 (2028-Q4)
• Intel Jaguar Shores timeline uncertain, possibly delayed to 2027 or later
• NVIDIA Rubin R200 is in full mass production; the Vera CPU + Rubin GPU combination is now shipping

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1. Qualcomm: Mobile Giant Moves Into Datacenter AI​

AI 100 → AI 200 → AI 250​

Qualcomm officially launched the AI 200 datacenter inference chip in October 2025, marking the mobile giant's formal entry into the datacenter AI market.

Model	Launch	Availability	Key Features
AI 100	2025-10	2026 H2	Rack-scale AI inference, 768GB LPDDR per card
AI 250	2025-10	2027 H1	Near-memory computing architecture, 10x effective memory bandwidth

Why Qualcomm Can Succeed​

1. Low TCO: LPDDR memory is far cheaper than HBM
2. Energy efficiency: Mobile chip design heritage, excellent power control
3. Inference-focused: Not chasing training performance, focused on inference scenarios
4. Rack form factor: Direct liquid cooling, 160kW rack-level power, Ethernet interconnect

Market Impact​

• Takes on NVIDIA H200: AI 200 inference performance approaches H200 but with 30-40% lower TCO
• Pressures NVIDIA: May push NVIDIA to launch inference-specific chips (e.g., Rubin CPX)
• Diversifies choice: Breaks NVIDIA's monopoly in the inference market

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2. AMD MI400 Series: Three Models, Precise Positioning​

At CES 2026 (January 2026), AMD officially unveiled the three models of the MI400 series, precisely covering different markets:

MI430X (HPC + Sovereign AI)​

Feature	Spec
Positioning	HPC + sovereign AI
FP32/FP64	Supported (key differentiator)
Use cases	Scientific computing, climate simulation, national AI infrastructure
Competitor	NVIDIA does not make FP64 AI cards

MI440X (Enterprise Servers)​

Feature	Spec
Positioning	Enterprise 8-GPU servers
Compatibility	Works with existing datacenter infrastructure
Use cases	Enterprise AI, private cloud, edge inference
Advantage	Cheaper and easier to deploy than MI455X

MI455X (Flagship AI Training)​

Feature	Spec
Positioning	Flagship AI training + inference
Optimized precision	FP4/FP8/BF16
Helios rack	Core component
Competitor	NVIDIA Rubin R200

Helios Rack-Scale Solution​

AMD also launched the Helios rack-scale AI solution at CES 2026:

• 18 Zen 6 CPUs (2nm process)
• 72 MI455X GPUs
• Direct liquid cooling
• Shipment expected in 2026 H2

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3. Huawei Three-Generation Roadmap: 950 → 960 → 970​

Huawei unveiled its three-generation chip roadmap at HC 2025 (September 2025) with a very clear timeline:

Ascend 950 Series (2026)​

Model	Launch	Key Features
950PR	2026-Q1	PR (inference-optimized), already in mass production
950DT	2026-Q4	DT (Decode + training), expected to scale up

Technical highlights:

• Added FP8/MXFP8/MXFP4 support
• Interconnect bandwidth 2TB/s (2.5x over 910C)

Ascend 960 (2027-Q4)​

• Doubled compute: All specs double versus the 950 series
• FP8: ~2 PFLOPS expected
• Process: N+3 (equivalent to 5nm)
• Positioning: Targets NVIDIA B200

Ascend 970 (2028-Q4)​

• Third-generation flagship: Only timeline announced, specs TBD
• Significance: Huawei's first complete generation-spanning roadmap
• Signal: China's domestic AI chips have entered a "roadmap-driven" phase

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4. Intel Jaguar Shores: Timeline Uncertain​

Original Plan​

• Launch: 2026
• Architecture: Xe-HPC + Gaudi fusion
• Process: 18A (Intel's most advanced)
• Memory: Possibly HBM4E (instead of originally planned HBM4)

Latest Developments​

• Possible delay: Some sources suggest a slip to 2027
• Competitors: AMD MI400 already unveiled, NVIDIA Rubin in mass production
• Market pressure: Intel is losing ground in the AI chip market; Jaguar Shores is its last chance

Impact on Roadmap​

If Jaguar Shores slips to 2027, Intel will essentially be out of the AI chip market.

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5. NVIDIA Rubin Platform: Full Mass Production​

Rubin R200 (2026-Q2 full mass production)​

Feature	Spec
HBM	288GB HBM4
Compute	50 PFLOPS FP4
NVLink	NVLink 6 (1800 GB/s)
Process	TSMC 4NP

Rubin NVL72 Cabinet (2026 H2 shipment)​

• 72 Rubin GPUs
• 36 Vera CPUs
• 1.8 EFLOPS FP4
• Direct liquid cooling

Vera CPU (Debut)​

• Architecture: Custom CPU replacing Grace
• Positioning: Deep co-design with Rubin GPU
• Significance: NVIDIA's transformation from a GPU company into a computing platform company

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6. Google TPU v8: Training/Inference Officially Split​

TPU 8t (training) + TPU 8i (inference)​

At Cloud Next 2026, Google announced TPU v8 would officially split into training and inference versions:

Feature	TPU 8t (training)	TPU 8i (inference)
Optimization	High compute, high bandwidth	Low latency, low cost
Interconnect	Optical interconnect	Ethernet
Launch	2027	2027

Significance​

• Industry trend: Specialization of training/inference chips
• Followers: Qualcomm AI 200 is also inference-only
• NVIDIA pressure: Does it need an inference-specific chip?

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7. Cerebras WSE-4: Wafer-Scale Engine Evolves​

Core Specs​

Feature	Spec
Transistors	1.4 trillion
Compute	125 PFLOPS FP8
Launch	2026 H2
Process	TSMC 5nm

Competitive Advantages​

• Massive model training: A single WSE-4 can train 10T+ parameter models
• Low-latency inference: Entire model on one chip, no communication overhead
• Mature software stack: Cerebras stack already supports PyTorch, TensorFlow

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8. Market Landscape Analysis​

Training Market​

Rank	Vendor	Product	Market Share (est.)
1	NVIDIA	Rubin R200	70%
2	AMD	MI455X	15%
3	Google	TPU v8t	10%
4	Huawei	Ascend 960	5% (mostly China)

Inference Market (New Battlefield)​

Rank	Vendor	Product	Advantage
1	NVIDIA	H200 / Rubin CPX	Mature ecosystem
2	Qualcomm	AI 200	Low TCO
3	AMD	MI440X	Good compatibility
4	Intel	Gaudi 4	Low price

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9. Key Trends​

Trend 1: Rise of Inference-Specific Chips​

• Qualcomm AI 200: Mobile giant enters the market
• NVIDIA Rubin CPX: NVIDIA's first inference-specific chip
• Google TPU 8i: Training/inference officially split

Trend 2: Rack-Scale Solutions Become Standard​

• NVIDIA NVL72: 72 GPU + 36 CPU
• AMD Helios: 18 CPU + 72 GPU
• Qualcomm rack: 160kW liquid-cooled rack

Trend 3: China's Domestic Chips Enter "Roadmap-Driven" Phase​

• Huawei three-generation roadmap: 950 → 960 → 970
• Clear timeline: 2026-Q1 → 2027-Q4 → 2028-Q4
• Significance: From "catch-up" to "planning"

Trend 4: HBM Capacity Becomes the Bottleneck​

• SK hynix: HBM4 capacity already booked by NVIDIA
• Samsung: HBM4E samples delivered to AMD
• Impact: MI400 and Rubin R200 shipments constrained by HBM capacity

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10. Procurement Recommendations​

If Procuring in 2026 H2​

1. Training scenarios:

   • First choice: NVIDIA Rubin R200 (best performance)
   • Alternative: AMD MI455X (better price/performance)
   • Domestic: Huawei Ascend 950DT (China-based customers)

2. Inference scenarios:

   • First choice: NVIDIA H200 (mature ecosystem)
   • Best value: Qualcomm AI 200 (if available)
   • Cost-sensitive: AMD MI440X

3. HPC scenarios:

   • Only choice: AMD MI430X (FP64 support)

If Procuring in 2027​

• Wait for Rubin Ultra: Performance possibly 2x R200
• Watch MI500: AMD's next-generation product
• Evaluate TPU v8: If already on Google Cloud

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Conclusion​

2026 H2 will be the most fiercely contested half-year in AI chip market history:

• NVIDIA continues to lead, but its advantage is narrowing
• AMD precisely positions three models; market share will keep rising
• Qualcomm enters the inference market; its low-TCO strategy may disrupt the market
• Huawei has a clear three-generation roadmap; domestic substitution accelerates
• Intel's Jaguar Shores is make-or-break

For procurement decision-makers, this is the hardest time to decide — every option has clear pros and cons.

For engineers, this is the best of times — chip performance doubles yearly, architectural innovation is endless.

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References​

• AI Compute Card Future Roadmap - MirrorFrog real-time updates
• NVIDIA Rubin R200 deep dive (see related articles on this site)
• AMD MI400 series CES 2026 launch (see related articles on this site)
• Qualcomm AI 100 launch analysis (coming soon)

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Last updated: 2026-06-20
Author: Charles Qing
Tags: #roadmap #market-analysis #procurement

On June 1, 2026, NVIDIA founder and CEO Jensen Huang officially announced at COMPUTEX 2026 (Taipei) that: the Vera Rubin platform has entered full production. This marks a fundamental paradigm shift for AI hardware from "discrete accelerators" to "integrated AI factories."

Key Highlights​

• Rubin GPU: Next-gen AI compute chip, FP4 compute is 3.6× that of Blackwell
• Vera CPU: 88 custom Arm cores (176 threads), replacing the Grace CPU
• NVLink 6: GPU-to-GPU interconnect bandwidth reaches 260 TB/s (double Blackwell)
• CX8 SuperNIC: 800Gb/s network, ConnectX-9 link reaching 28.8 TB/s
• HBM4 memory: 288GB per chip, 13 TB/s bandwidth
• Agentic throughput: 10× over Grace Blackwell

Complete Vera Rubin Platform Specs​

Vera Rubin is not a single GPU but a complete AI factory platform comprising 7 chips:

Chip	Type	Purpose
Rubin GPU	Main AI compute chip	Training + inference
Rubin Ultra GPU	Flagship version	Ultra-scale inference
Vera CPU	CPU paired with Rubin	Host CPU + data preprocessing
NVLink 6	Interconnect chip	High-speed GPU interconnect (260 TB/s)
CX8 SuperNIC	NIC	800Gb/s network
XDR 800G switch	Datacenter network	Cross-rack communication
Rubin Platform POD	Whole cabinet	Pre-configured AI factory (144 GPUs)

Rubin GPU Detailed Specs (estimated)​

Parameter	Rubin GPU	Rubin Ultra	Blackwell (B200)
Architecture	Rubin	Rubin Ultra	Blackwell
Process	TSMC 3nm (est.)	TSMC 3nm	TSMC 4NP
Memory	288GB HBM4	288GB HBM4E (est.)	192GB HBM3e
Memory bandwidth	13 TB/s	13+ TB/s	8 TB/s
FP4 compute	~3,600 TFLOPS (est.)	~5,000 TFLOPS (est.)	2,250 TFLOPS
TDP	1,000W (est.)	1,200W (est.)	700-1000W
Interconnect	NVLink 6 (260 TB/s)	NVLink 6	NVLink 5 (1800 GB/s)
Mass production	2026 Q3	H2 2027	2024 Q4

📌 Note: Rubin's exact specs are not fully public yet; some values above are estimates.

Vera CPU: The New Host CPU Replacing Grace​

Vera CPU is NVIDIA's self-designed Arm-architecture CPU, replacing the previous Grace CPU:

Parameter	Vera CPU	Grace CPU
Cores	88 cores (176 threads)	72 cores (144 threads)
Architecture	Custom Armv9 (est.)	Arm Neoverse V2
Interface	NVLink 5.0 (1.8 TB/s)	NVLink 4.0 (900 GB/s)
TDP	~500W (est.)	350-500W
Purpose	AI factory Host CPU	HPC / AI Host

Key upgrade: Vera's co-design with the Rubin GPU achieves end-to-end optimization in compute, data loading, and preprocessing, comparable to Google TPU 8t's Arm Axion integration.

Performance vs Blackwell​

NVIDIA officially claims that under the same POD configuration (144 GPU chips):

Metric	Grace Blackwell (GB200 NVL72)	Vera Rubin NVL144	Improvement
FP4 compute	1.1 PFLOPS	3.6 PFLOPS	3.3×
Memory capacity	288GB×72 = 20.7TB	288GB×144 = 41.4TB	2×
Memory bandwidth	8 TB/s×72	13 TB/s×144	~3.3×
NVLink bandwidth	1800 GB/s×72	260 TB/s (full POD)	~2×
Agentic throughput	Baseline	10×	10×
Performance per watt	Baseline	25× (vs CPU alone)	25×

💡 Why "10× agentic throughput"? Agentic AI workloads differ from training/inference: one prompt may trigger multiple stages including reasoning, retrieval, tool calls, and response generation, involving thousands of steps. The Rubin platform is optimized for this long-chain, high-concurrency workload.

MGX Third-Gen Rack-Scale System​

Vera Rubin adopts the MGX third-gen open rack-scale system design:

• Five-rack synergy: Vera Rubin NVL72 system + Vera CPU + Groq 3 LPX + Vera BlueField-4 STX storage + Spectrum-6 SPX Ethernet
• Global supply chain: 30 countries, 350+ factories, hundreds of partners (Dell, HPE, Lenovo, Supermicro, Asus, Foxconn, etc.)
• Spectrum-X Ethernet silicon photonics: World's first switch based on CPO (co-packaged optics) supporting 200Gb/s SerDes, now in mass production

Mass Production Timeline​

Time	Event
Jan 2026	CES 2026 first unveils Rubin platform
June 1, 2026	COMPUTEX 2026 announces full production
Fall 2026	Vera Rubin officially starts mass production and shipment
H2 2027	Rubin Ultra launch (HBM4E upgrade)
2028	Feynman architecture (next gen)

AI Factory: From Selling Chips to Selling "Smart Production Lines"​

Huang said something at the launch that shook the industry:

"Rubin's Agentic AI throughput is 10× that of Blackwell. Rubin is a complete AI factory platform."

This marks a fundamental shift in NVIDIA's business model:

• Past: Sold GPUs (H100/B200), customers built systems themselves
• Now: Sells "complete AI factory solutions" (Vera Rubin POD), including GPU, CPU, network, storage, software stack
• Future: Becomes the "TSMC" of global AI infrastructure (providing smart production capacity)

vs Competitors​

Vendor	Product	Positioning	Advantage	Disadvantage
NVIDIA	Vera Rubin	Complete AI factory solution	Most complete ecosystem, most mature software	Expensive, extremely high power
AMD	MI455X (MI400 series)	Training competitor	Price/performance, open ecosystem	Software ecosystem gap
Google	TPU 8i/8t	Cloud training/inference	Deep Gemini integration	Google Cloud only
Huawei	Ascend 910C/950	Domestic substitution	China localization, AscendMind framework	Affected by export controls

Industry Impact​

1. AI labs: Frontier model training time shrinks from "months" to "weeks"
2. Cloud providers: Must decide whether to procure Vera Rubin POD (conflicts with self-developed chip strategy)
3. Hyperscale datacenters: AI factory becomes a new competitive dimension (whoever has the strongest compute can train the strongest model)
4. Domestic chips: Ascend 910C/950, Cambricon MLU590, etc. must catch up to Blackwell in 2026-2027, or the gap will widen to the Rubin era

Related Chips​

• NVIDIA Rubin R200 - Rubin architecture GPU detailed specs
• NVIDIA Vera CPU - Vera CPU detailed specs
• NVIDIA B200 - Previous-gen Blackwell architecture
• AMD MI455X - Direct competitor (MI400 series)

References​

• NVIDIA Blog: Vera Rubin Full Production
• COMPUTEX 2026 Keynote
• NVIDIA Official Newsroom

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This article is compiled from NVIDIA official announcements and public materials. Some specs are estimates, subject to final official release.