14 posts tagged with "NVIDIA"

This article is based on market analysis published by Bloomberg Intelligence and Bernstein in September 2026 and public reporting; market share and revenue figures are analyst estimates, not official disclosures.

On September 28, two Wall Street reports simultaneously painted a dramatic picture: the balance of market share in China's AI compute market completed an almost total flip within 12 months.

1. The Share Flip: 40% to 8%, Ascend to 50%​

Bernstein's latest forecast:

• NVIDIA's share of the China AI chip market will fall from about 40% to about 8% by the end of this year
• Huawei Ascend rises to nearly 50%
• The immediate trigger: China's September ban on new H20 orders from NVIDIA, which shut the last channel for NVIDIA's return to the Chinese market
• ByteDance, Alibaba, and Tencent have all placed large Ascend orders

On the timeline, this was not a sudden shock but the cumulative result of three years of tightening export controls: NVIDIA's share of the China AI chip market once peaked at 95%; as high-end chips were cut off, Chinese hyperscale cloud providers pivoted wholesale to Huawei and domestic alternatives. Even when Washington allowed H200 sales to China in January 2026, the gears of that shift had already meshed — there was no going back.

2. Ascend 950PR: The "Chinese H200" in Analysts' Eyes​

What underpins this share data is product strength itself:

• The Ascend 950PR entered mass production in March this year, with FP4 compute of up to 2 PFLOPS and 128GB of domestic HBM
• Analysts rate it as roughly on par with the NVIDIA H200
• Huawei's AI chip revenue is expected to reach $12 billion this year, up 60% from $7.5 billion in 2025

For the full specifications of the 950 series, see our earlier in-depth articles: Ascend 950PR/950DT Dual-Configuration Analysis and Ascend 960 Official Launch — the 960 was ready three quarters ahead of schedule, confirming a one-generation-per-year cadence.

3. The Model Side: Chinese Open Models Take the OpenRouter Token Pie​

While chip shares flipped, the model usage data is equally striking (OpenRouter platform statistics):

Metric	Data
DeepSeek token share (June)	16.3%, surpassing Google, Anthropic, and OpenAI individually to rank first
Combined token share of Chinese open-weight models (May)	About 61% (DeepSeek, Qwen, MiniMax, Tencent Hunyuan, etc.)
Weekly token consumption of Chinese models	About 18 trillion, versus about 5.5 trillion for US models — a gap of more than 3x, with the overtake completed within a year
China-US frontier model performance gap (June)	Narrowed to 6%, a historic low (9% in May)

Compute and models form a positive feedback loop: cards that cannot be bought force domestic compute to scale up; scaled-up domestic compute produces cheap tokens; and cheap tokens let Chinese open-source models swallow the bulk of global inference traffic.

4. But the Stock Market Isn't Buying It​

Bloomberg Intelligence pointed out a contradiction in the same period: the valuation discount of the China Tech 8 relative to the US Magnificent Seven has widened to more than 50%, the widest of the year, and BI believes only a "true AI breakthrough" can close it. Year-to-date stock performance: Alibaba about -7%, Tencent about -23%, while US AI infrastructure leaders broadly gained more than 15%.

There are two readings of this divergence: either the market is underestimating China's AI fundamentals, or earnings execution (Alibaba's EPS missed expectations by 17.3% last quarter, Baidu's by 36%) has dragged down the delivery of the AI narrative. For industry observers, the notable point is: the compute-side data (share, revenue, shipments) has moved ahead, while application-side monetization is still on the way.

5. Three Takeaways for Compute Buyers​

1. For deployments in China, the Ascend ecosystem is already the default option. The cost of migrating from CUDA to CANN is one-time, while supply uncertainty is persistent; after the September ban, there is no compliant path to procuring new NVIDIA cards in the Chinese market.
2. Domestic compute "matching the H200" is a watershed. The implicit assumption of domestic substitution used to be "discounted performance, discounted price"; when single-card performance catches up to the H200 generation, procurement decisions return to pure TCO and supply-security calculations — we recommend using the TCO Calculator to put electricity, depreciation, and utilization into the same table.
3. The token cost curve determines the application landscape. Chinese models' 61% share of OpenRouter tokens shows that the chain of compute self-sufficiency leading to token price drops leading to application prosperity has completed its first leg; the next question is whether inference costs can keep falling.

Summary​

From 40% to 8% is not a slogan but a market reshuffle driven jointly by the ban, product strength, and the model ecosystem. For the Chinese market, the mass-production cadence of Ascend 950/960 and the maturity of the CANN ecosystem will determine whether this share can be held; for the global market, the combination of China's compute "internal circulation + open-source models going overseas" is rewriting the geographic distribution of inference traffic.

(Market share and revenue forecasts come from Bernstein / Bloomberg Intelligence analyst reports; actual figures are subject to each company's financial reports.)

This article is based on NVIDIA official product pages, the March 2026 GTC architecture blog, and third-party benchmark data; performance figures are vendor architecture comparisons, and actual gains should be verified with your own tests.

NVIDIA has confirmed that Groq 3 LPX — the "seventh chip" of the Vera Rubin platform — has entered full mass production, manufactured at Samsung's Pyeongtaek campus. This is the first time the deal has landed in the form of production silicon since December 2025, when NVIDIA spent roughly $20 billion to obtain a non-exclusive IP license to Groq plus its core engineering team.

For the inference hardware landscape, this is a paradigm-level event: for the first time, NVIDIA has incorporated a "specialized inference architecture defined by someone else" into its own flagship platform — and not as an add-on sale, but as deep co-design.

1. The Groq 3 LPU Chip and the LPX Rack: Specs at a Glance​

Single Groq 3 LPU (4nm, Samsung foundry):

Item	Value
Compiler-managed on-chip SRAM	500 MB
SRAM bandwidth	150 TB/s
Chip-to-chip scale-up bandwidth	2.5 TB/s (96 chip-to-chip links, 112 Gbps each)

A single LPX rack (32 1U liquid-cooled trays, 8 LPUs per tray):

Item	Value
Total LPUs	256
FP8 compute	315 PFLOPS
Total on-chip SRAM	128 GB
Aggregate SRAM bandwidth	40 PB/s
In-rack scale-up bandwidth	640 TB/s
DDR5 memory	12 TB (hosting large model weights)

The 500 MB of SRAM per LPU may not look like much, but multiplied by 256 LPUs and stacked with 40 PB/s of aggregate bandwidth, it forms the physical foundation of "deterministic low-latency decoding" — the LPU's design philosophy is precisely to use compiler static scheduling of on-chip SRAM to completely eliminate memory-fetch stalls during the inference decoding phase, which is exactly the most typical bottleneck of GPU inference.

2. AFD: Attention and FFN Split Up, GPU and LPU Each Do Their Own Job​

LPX does not replace the GPU; instead, it forms a heterogeneous system with Vera Rubin NVL72, centered on AFD (Attention-FFN Disaggregation):

1. Rubin GPUs handle prefill and attention — building the KV cache over large contexts and executing attention layers, consuming HBM capacity and high throughput;
2. Groq 3 LPUs handle FFN / MoE expert-layer decoding — latency-sensitive and pattern-predictable, exactly the home turf of deterministic SRAM scheduling;
3. Intermediate activations are exchanged between the two engines token by token, orchestrated and routed by NVIDIA Dynamo: the GPU computes every attention layer, the LPU computes every feed-forward layer, jointly producing each output token.

The logic of this division of labor is clear: agentic AI applications can consume 15x the tokens of traditional AI applications, and the bottleneck shifts from "can it finish computing" to "can it keep emitting tokens at stable low latency." Let the big HBM container run attention, and let the deterministic SRAM engine run decode — each plays to its strengths.

3. Measured Results and Official Figures​

• Third-party benchmarks (Artificial Analysis): with Gemma 4 31B at a 100K token context, LPX output reaches roughly 3400 tokens/s — inter-token intervals below 1 millisecond, a qualitative leap in interactivity for long-context agentic scenarios
• Official architecture comparisons: with LPX added, Vera Rubin NVL72 achieves up to 35x higher throughput per megawatt on trillion-parameter models; up to 10x more revenue opportunity per watt in "high-value token" scenarios
• Launch customers: Nebius is the first to deploy LPX racks to expand its token capacity; CoreWeave already connects Vera Rubin racks in production with Spectrum-X Multiplane

It must be emphasized: the 35x/10x figures are architecture comparisons at specific high-interaction operating points, not universal conclusions. For training, high-throughput batch inference, and workloads that need CUDA ecosystem flexibility, the GPU remains the right answer; LPX's home turf is scenarios where "single-user interactive latency is the product" — agent loops, real-time coding assistants, long-context conversations.

4. Three Industry Signals​

1. Specialized inference chips get absorbed, not opposed. The old narrative of the LPU as a "GPU challenger" has become part of Vera Rubin. The endgame for inference hardware may not be one architecture winning, but the heterogeneous combination of "GPU + specialized decoding engines" becoming the standard. For other inference chip startups (Cerebras, Etched, etc.), this is both proof that the ceiling has risen and a warning: get integrated or find differentiation.

2. Samsung foundry lands a high-end AI order. Against the backdrop of TSMC's near-monopoly on AI main chips, Samsung 4nm taking on LPX mass production is highly significant — combined with Tesla's earlier AI6 2nm order, Samsung foundry has a shot at returning to full-year profitability in 2027.

3. Inference economics enters the "priced per MW" era. When vendors start telling their story with tokens/MW and revenue per watt, the core KPI of compute selection has completely shifted from peak compute (TFLOPS) to token output per unit of energy. This is consistent with the power-and-electricity cost model built into our TCO Calculator: the chip with the best-looking peak specs is not necessarily the chip with the lowest cost per token.

Summary​

Groq 3 LPX mass production marks the arrival of a heterogeneous era for inference hardware: "GPUs manage throughput, LPUs manage latency." For teams currently selecting inference clusters, the recommendation is to evaluate workloads separately: keep batch offline inference on GPUs, and separately calculate the unit cost of LPX-class solutions for interactive long-context agents. If in doubt, run the 3-year total cost of ownership of both architectures through the TCO Calculator before deciding.

(Performance data in this article comes from NVIDIA official architecture comparisons and Artificial Analysis third-party benchmarks; for actual deployments, please rely on your own testing.)

On September 16, MLCommons released the MLPerf Inference v6.1 Closed Division results, and NVIDIA's Vera Rubin NVL72 completed its benchmark debut. The same day, CoreWeave announced that a multi-rack Vera Rubin cluster was live on its cloud — a "rent the new hardware on launch day" cadence that is compressing the cycle from next-generation compute announcement to billable output down to a quarter.

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1. Debut Results: 3.7x and 2.5x​

NVIDIA, via preview submissions (entries 6.1-0106 / 6.1-0074), provided an apples-to-apples comparison of its two flagship generations:

Benchmark Model	Vera Rubin NVL72 vs GB300 NVL72	Software Stack
Qwen3-VL-235B-A22B (235B multimodal MoE)	Throughput up to 3.7x (across offline / server / interactive scenarios)	vLLM + NVIDIA Dynamo
DeepSeek-R1-671B (671B inference model)	Throughput up to 2.5x	TensorRT-LLM

The three technologies behind these numbers:

• NVFP4 precision: compresses the memory footprint of model weights, attention tensors, and the KV Cache, enabling significantly larger effective batch sizes;
• Disaggregated serving: prefill (compute-intensive) and decode (bandwidth-intensive) are split across separate GPU pools, each independently optimized;
• Expert parallelism: MoE expert layers route across chips in a distributed fashion, paired with sixth-generation NVLink / NVLink Switch (NVIDIA claims 10x the packet rate of commodity Ethernet at 3x lower latency).

2. Same-Session Highlights: Scaling Efficiency and the Software Dividend​

• GB300 four racks, 288 chips, 99% scaling efficiency: in the DeepSeek-R1 offline scenario, scaling from a single rack of 72 chips to 4 racks of 288 chips shows almost no loss (entries 6.1-0073 / 6.1-0074) — the first time rack-scale interconnect scaling efficiency has been validated at the 288-chip level;
• The software dividend is still being paid out: on the same GB300 hardware, v6.1 software optimizations deliver up to 1.6x Qwen3-VL gains over v6.0; NVIDIA also reported post-submission gains for GPT-OSS-120B and DLRMv3 (not verified by MLCommons);
• 19 partners submitted, 8 of them using multi-node Blackwell NVL72 configurations (ASUS, Azure, Cisco, CoreWeave, Crusoe, Dell, Fujitsu, HPE, Lambda, Nebius, OCI, Supermicro, and others); Nebius also submitted Vera Rubin preview results.

3. CoreWeave Online the Same Day: Rentable at Launch​

On the same day the MLPerf results were published, CoreWeave announced that its multi-rack Vera Rubin NVL72 cluster was live on its cloud:

• Spectrum-X networking links hundreds of Rubin GPUs into a single scale-out cluster, with each GPU paired with 2 ConnectX-9 SuperNICs (1.6Tb/s scale-out bandwidth);
• The AI object store LOTA cuts read latency by 8x;
• On the operations side: Valvey software-defined liquid cooling (NVIDIA spec: 45°C liquid inlet), the Racky rack control layer, and Rack LifeCycle Controller manage an entire NVL72 rack as a single programmable entity;
• Back in July, CoreWeave's own testing put Vera Rubin at 10x tokens/s/MW versus GB200 NVL72 on DeepSeek R1 (company figures, not MLCommons-verified).

4. The Competitive Picture​

• AMD + Crusoe: set MLPerf's all-time high aggregate throughput of 5.75M tokens/s on 512 chips (AMD had the broadest submission coverage this round);
• SemiAnalysis AgentX preview: Vera Rubin up to 30x over GB300 on agentic workloads (preview figures); the MLPerf Endpoints benchmark is forthcoming and will bring agentic inference into standardized measurement;
• Pending validation: Vera Rubin results are preview submissions awaiting independent reproduction; no quantified quality metrics were given for NVFP4's "virtually lossless" claim; per-token cost and power-consumption scaling comparisons have not been published. Matching submissions from Google TPU v7 and AMD MI455X UALoE72 are expected within 2026.

On-site spec comparisons: Rubin R200 (288GB / 22TB/s), B300 Ultra (GB300-class core).

5. Takeaways​

• Vera Rubin NVL72 debut: Qwen3-VL 3.7x, DeepSeek-R1 2.5x over GB300 NVL72 (preview figures);
• GB300 across four racks of 288 chips at 99% scaling efficiency — rack-scale interconnects have entered the usable range;
• CoreWeave brought a multi-rack cluster online the same day — the cycle from next-gen compute launch to billable output is now measured in quarters;
• What to watch: independent reproductions and formal (non-preview) submissions, TPU v7 / MI455X comparison results, and measured per-MW token throughput.

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Further Reading​

• Rubin R200 Spec Page / B300 Ultra Spec Page (this site)
• NVIDIA Vera Rubin Mass Production and Liquid Cooling Deployment
• Hot Chips 2026 Full Recap: Rubin, MI455X, Crescent Island on the Same Stage

References​

• NVIDIA Blog: Vera Rubin NVL72 Makes Its First Appearance in MLPerf Inference v6.1 (2026-09-16)
• MLCommons: MLPerf Inference v6.1 Closed Division results (entries 6.1-0073 / 6.1-0074 / 6.1-0106)
• CoreWeave Investor Relations: multi-rack Vera Rubin NVL72 availability announcement (2026-09-16)
• AMD Blogs: MLPerf Inference v6.1 submission results

This article is compiled from public MLCommons results and vendor official statements. Vera Rubin results are preview submissions; some gain figures are not MLCommons-verified and are flagged item by item.

本周（2026 年 9 月 1 日–5 日）AI 算力行业的题眼，是两条相反方向的成本重构：海外，英伟达以史上最大并购吞下开发者生态入口，同时给旗舰减配显存——"内存太贵"倒逼硬件从单卡堆料走向系统级互联；国内，DeepSeek 16 万颗昇腾订单把"国产替代"从口号变成头部实验室的资产负债表决策，字节近 300 亿美元融资为算力扩张装上杠杆。

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1. DeepSeek 拟购 16 万颗昇腾 950DT：国产算力的"标志性订单"​

彭博社 9 月 4 日报道，DeepSeek 计划在内蒙古乌兰察布新建的约 1GW 数据中心部署至少 16 万颗华为昇腾 950DT，主要用于推理而非训练。按每颗约 11.1 万元的市场价估算，订单总额约 178 亿元人民币（约 25.6 亿美元）——这是迄今已知规模最大的昇腾集群，是半年前深圳首个万卡级集群的 16 倍。

三个关键读数：

• 主动选择，而非被迫替代：DeepSeek 是公认最会"榨干"算力的实验室。创始人梁文锋 7 月曾直言：华为超节点能完成 GB300 的任务、延迟没有明显差别，但约需 4 颗昇腾才抵 1 颗英伟达、技术上落后约两年。选择昇腾跑推理，是在综合成本、供应链安全与本土化后的理性决策——推理对软件生态依赖较浅，正是国产芯片的突破口；
• 瓶颈在供给端：受高端内存（HBM）短缺制约，昇腾 950DT 今年产量仅数十万颗（2026 年全部昇腾 die 计划约 160 万颗），DeepSeek 希望加购更多但产能所限，整单交付或需一年以上——国产 HBM 与先进封装成为整条链的胜负手；
• 过渡性押注：DeepSeek 同时在与中芯国际合作开发自研推理芯片，并于 6 月完成约 500 亿元融资、继续洽谈数十亿美元基建融资。国产算力的终局是多元自主，而非单一依赖。

单颗 950DT：144GB HBM、4.0TB/s 带宽、2.0TB/s 互联，原生支持 FP8/FP4/HiF8，详见昇腾 950DT 规格页。

2. 英伟达 129.3 亿美元收购 Hugging Face：买下"铲子的交易所"​

当地时间 9 月 3 日，英伟达宣布以 129.3 亿美元收购全球最大开源 AI 平台 Hugging Face，超过 2020 年 69 亿美元收购 Mellanox，成为其史上最大并购。交易含约 119 亿美元股权款与最高约 10 亿美元员工留任计划，预计 2027 年上半年完成，待监管批准。

Hugging Face 托管超 300 万个模型、50 万个数据集，服务超 1800 万名开发者。黄仁勋承诺平台继续开放中立运营：不强制绑定英伟达资源、开源属性完整保留。

解读：算力霸主的护城河从"芯片 + 网络 + 软件栈"一路修到了"模型分发 + 开发者生态"——卖铲人开始收购铲子的交易所。平台的"中立性"承诺能否兑现，将成为全球监管与竞争性云厂商持续盯防的焦点；对国内产业而言，模型托管、权重分发这类"轻资产 AI 基础设施"与芯片一样，正在成为大国科技博弈的卡点。

3. Rubin Ultra 显存减配：内存占 TCO 40% 后的算术题​

SemiAnalysis 最新报告（科创板日报 9 月 3 日转引）显示，英伟达已将旗舰 Rubin Ultra 的 HBM 配置从 HBM4E 12-Hi（384GB 档）下调至 HBM4 8-Hi（192GB），三星正配合开发 8 层产品。

• 动因：HBM/DRAM 涨价后，内存已占整机 TCO 约 40%；减配后 HBM 成本降超 50%，即便计入 2026 年 HBM 涨价预期，内存占总资本开支比例也将从 40% 压至 28%；
• 钱去了哪：转向 Scale-up 纵向扩展网络——以 NVL576 NPO 方案测算，光模块取代机架间互连后，Scale-up 网络占机架总支出比例从 4% 升至 12%；
• 连锁反应：TrendForce 显示英伟达自 2026 Q3 起并行评估 HBM4E 8-Hi / 12-Hi / HBM4 8-Hi 多套方案，部分云厂商也在考虑下调下一代自研 ASIC 的 HBM 容量。

连定价权最强的英伟达都给旗舰"减配求量"，等于官宣：当前 AI 硬件最紧的约束是内存（美光高管称新增内存供应 2028 年前难有实质放量），单卡堆料的军备竞赛告一段落，硬件价值重心正迁移到光互联、CPO、高速交换与 PTFE 背板。华泰测算 2027 年存储供需缺口将从约 -7% 收窄至 -3%——上行周期未逆转，但从"普涨"走向"结构性紧缺"。

详见本站已同步更新的 Rubin Ultra 规格页与HBM4 量产竞速分析。

4. 推理 ASIC 军备提速：谷歌"一年两款"，Jalapeño 规格落地​

• 谷歌 TPU 迭代周期从两年一代压缩至"每年两款"（华创证券 9 月 4 日研报）：第八代已拆分为训练（8t）与推理（8i）双架构，8i 把内存/算力配比拉到 8t 的 1.65 倍，专为推理放量设计；
• OpenAI Jalapeño 规格披露：6 堆栈 HBM4 共 216GB、带宽 15.4TB/s、700W，围绕投机解码设计；OpenAI 称在 DeepSeek R1 负载下 tokens/kW 达 GB300 的 1.7 倍；RTL 冻结到流片 9 个月，首批硅片后约 10 周承载 ChatGPT 流量。详见规格页（本站已更新）；
• workload-specific 时代开场：训练、推理、推荐各自长出专用芯片，上游 HBM/封装/光互联的供应节奏必须跟上"半年一代"。

5. 国内动态：字节 296 亿美元加杠杆，摩尔线程 Token 超节点投产​

• 字节跳动获约 296 亿美元融资安排（彭博 9 月 3 日），较最初约 200 亿美元目标大幅上调，用于数据中心与 AI 基建；另据产业报道正洽谈在内蒙古新增 5-6GW 算力产能——中国 AI 公司迄今最大规模基建融资之一，算力正被当作可融资、可证券化的重资产经营；
• 摩尔线程 × 趋境科技 "Token 超节点"投产（光明网 9 月 4 日）：以 MTT S500 承担 Prefill 与 KV Cache 生成、高带宽 GPU 专注 Decode 的 PD 异构方案，实测平均生成速度超 50 TPS、KV Cache 命中率超 90%、稳定性 99.9%，已承接头部模型厂商官方业务流量——超节点竞争维度从"单卡参数"转向"单位 Token 生产成本"；
• OpenAI 发布 GPT-6 Astra（9 月 4 日）：超 10 万颗 GPU 在 Stargate 集群完成训练，推理放量与超大规模集群仍是全球算力叙事主线；
• SemiAnalysis 基准：AMD MI355X 新提交在 AgentX 基准低交互区间tokens/$ TCO 击败 B300——vLLM + LMCache 软件栈的贡献首次被独立机构量化认可。

6. 市场：中美算力资产一涨一调​

美东 9 月 4 日，美国 8 月非农仅增 8.9 万人（预期 16 万），10 年期美债收益率回落至 3.78%，成长股走强：科技板块 XLK 周涨 4.2%，英伟达周涨 8.7% 收于 230.36 美元。A股 9 月 4 日反向回调：AI 算力芯片板块 -1.99%、服务器 -2.51%、超节点 -2.86%，浪潮信息跌停、寒武纪 -2.54%——基本面无恶化（博通、戴尔、中际旭创订单与财报持续验证景气），更多是交易层面获利兑现。

下周起三连催化密集：CIOE 光博会（9/9-11）→ 华为全联接大会（9/17-19）→ 云栖大会（9/22-24）。国产超节点从"发布会 PPT"到"批量交付"的成色，将迎来集中检验。

本周一句话​

内存太贵改变了所有人的算法：英伟达给旗舰减配显存、把钱投给互联；DeepSeek 用 16 万颗昇腾买推理确定性；谷歌把 TPU 迭代压到半年一代。2026 年 Q4 起，"每兆瓦/每美元 token 数"将取代"单卡 PFLOPS"，成为算力采购的第一指标。

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相关链接​

• 华为昇腾 950DT 规格页
• NVIDIA Rubin Ultra 规格页
• OpenAI Jalapeño 规格页
• NVIDIA Rubin 规格页

参考资料​

• 彭博社（转引）：DeepSeek 拟部署 16 万颗昇腾 950DT（2026-09-04）
• cnBeta/今日头条：DeepSeek 据称采购 16 万颗华为昇腾 950DT 芯片（2026-09-05）
• 科创板日报：SemiAnalysis 拆解 Rubin Ultra 减配（2026-09-03）
• Natural News/DailyAI：Nvidia To Acquire Hugging Face For $12.9B（2026-09-05）
• 光明网：摩尔线程 × 趋境科技 PD 异构推理方案投产（2026-09-04）
• AGI Hunt：AI News Daily 2026-09-05

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本文基于彭博社、科创板日报、SemiAnalysis、TrendForce、华创证券研报及光明网等公开报道整理。订单金额与市场数据为媒体/机构预估口径，实际以相关公司正式披露为准。

This article is based on official announcements from AWS and NVIDIA (September 5, 2026) and public statements by executives of both companies.

On September 5, 2026, AWS and NVIDIA announced an expanded strategic partnership: on top of the "1 million additional GPUs starting in 2026" plan announced at GTC 2026, they will deploy 2 million more NVIDIA GPUs, covering three architecture generations — Blackwell Ultra, Rubin, and Rubin Ultra — with a deployment window of 2027-2028. Demand growth exceeding all previous forecasts was the direct reason both companies cited.

This is no longer a simple "chip purchase" — it is a full-stack partnership spanning GPUs, CPUs, interconnect, memory, open-source models, and software. We break the key information into six points.

1. Composition and Timeline of the 2 Million GPUs​

• Scale: 2 million GPUs (added on top of the original 1 million GPU plan, tripling the total committed scale)
• Architectures: Blackwell Ultra, Rubin, Rubin Ultra
• Timeline: 2027-2028, deployed across AWS global infrastructure (including newly built AI factories)
• Context: Amazon's 2026 capital expenditure guidance has been raised from $200 billion to $220 billion, and CEO Andy Jassy has explicitly said it is still not enough to meet AI compute demand

For reference, the figures Jensen Huang gave at GTC 2026 put cumulative orders and demand for the Blackwell and Rubin platforms through 2027 on track to reach $1 trillion (at GTC 2025, the estimate for 2026 was roughly $500 billion). AWS's add-on order is one of the heaviest puzzle pieces in that big picture.

2. Vera CPU Comes to AWS for the First Time​

This is the most structurally significant change in the partnership: NVIDIA Vera CPU infrastructure will enter AWS.

The Vera CPU is the general-purpose processor in the Vera Rubin platform designed for agentic AI, positioned to efficiently turn AI resources into "completed agent tasks." As agentic workloads rise, CPU-side pressure on task orchestration, memory management, and data scheduling rises in step — pure GPU expansion is no longer enough, and AWS needs a matching high-performance CPU layer. This also aligns with AWS's strategy of "offering the broadest compute choices, from in-house chips (Graviton/Trainium) to partner chips": Vera does not replace Trainium, but fills in the CPU compute layer alongside the accelerated infrastructure.

3. NVLink Fusion × NVHBM: Open Architecture Goes Deeper​

At re:Invent 2025, AWS announced that its next-generation Trainium chip would support NVIDIA NVLink Fusion high-speed interconnect. This time, both companies took the partnership one step further:

• Amazon Annapurna Labs will support NVIDIA's new custom high-bandwidth memory NVHBM (developed in collaboration with memory vendors)
• Trainium thereby gains a faster, more power-efficient memory option
• Trainium and GPUs can work together within the same rack-scale architecture, sharing scale-up interconnect

For the chip industry, this is a signal worth watching closely: NVLink Fusion + NVHBM means NVIDIA's interconnect and memory technologies have started "supplying" competing ASICs. The boundary between the in-house ASIC camp (Trainium, TPU, MTIA) and the NVIDIA GPU camp is shifting from "either/or" to "hybrid deployment."

4. 100,000 GPUs: The U.S. Government Sovereign AI Factory​

A dedicated public-sector business is carved out of the partnership: AWS and NVIDIA will build AI factories for the U.S. government, deploying 100,000 GPUs on secure AWS infrastructure to host federal and national security workloads (Impact Level 6 and above), supporting the development of advanced AI models within strict regulatory frameworks.

Sovereign AI turning from a slogan into concrete numbers is a defining feature of this cycle — government customers are becoming first-class buyers of AI compute.

5. Software and Physical AI Deepen in Parallel​

Beyond hardware, the software layer of the partnership is also strengthening:

• NVIDIA Nemotron open-source models continue to arrive on Amazon Bedrock and SageMaker
• Amazon EMR data processing and OpenSearch vector indexing are accelerated by cuDF / cuVS
• Amazon Robotics officially adopts the NVIDIA physical AI platform (Jetson, Omniverse, Isaac) for warehouse automation and next-generation robotics

Physical AI (robotics, embodied intelligence) is becoming a new growth pole in cloud providers' compute narratives — the same trend as JD.com, Tesla, and others writing embodied intelligence into their compute procurement logic.

6. Implications for Compute Buyers​

Observation	Implication
Demand "beat all forecasts"	Supply tightness is not a short-term phenomenon; the 2027-2028 compute window must be locked in now
Mixed procurement across three architectures	During the Rubin/Rubin Ultra production ramp-up, Blackwell Ultra remains the delivery mainstay; procurement needs cross-generation planning
CPU layer revalued	agentic AI pushes the bottleneck from GPU to CPU orchestration and memory bandwidth; do not focus only on accelerator cards when selecting
Sovereign AI lands	Government-scale orders enter the market, further tightening the allocatable supply of high-end GPUs

For decision-makers weighing build versus rent, every massive add-on order from cloud giants reprices the future rental curve. If you are evaluating GPU purchase or rental options, we recommend running a quantitative calculation with the TCO Calculator: enter chip price, power draw, utilization, and rental rates to compare 3-year total cost of ownership.

Summary​

2 million GPUs, Vera CPU in the cloud, NVHBM opening up, 100,000 sovereign compute GPUs — this round of expansion between AWS and NVIDIA pushes the "AI factory" race into the full-stack era. Compute scarcity will most likely only tighten before 2027; whether you are buying, renting, or betting on domestic alternatives, locking in supply and cost curves early is the surest move right now.

(The data in this article comes from official AWS/NVIDIA announcements and public statements by executives of both companies; architecture performance figures are as released by the vendors.)

2026 年 9 月初，供应链信息确认：英伟达 Vera Rubin 平台已于 8 月正式量产、9 月启动批量出货，无延期、无卡顿。与 Blackwell 迭代初期的产能波折不同，这次量产节奏异常平稳——谷歌云、微软 Azure、CoreWeave、甲骨文云等头部云厂商已启动机架部署。但真正值得产业记住的，不是"又一代 GPU 量产了"，而是 Rubin 把液冷从"可选配置"变成了"硬性前置条件"。

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1. 量产节奏：史上最平稳的一次平台切换​

根据产业链调研与券商跟踪信息：

• 2026 年 8 月：Vera Rubin 正式量产；
• 2026 年 9 月：批量出货启动；
• 2026 下半年：CoreWeave、谷歌云、微软 Azure、甲骨文云机架部署落地；
• 2026 年：上代 GB 架构机柜出货量有望达 6 万台（同比翻倍）；
• 2027 年：GB 与 Rubin 两代平台合计出货体量有望接近 10 万台，Rubin 新机柜远期产能目标为每天 1000 个 NVL72 机柜。

需求侧同样在加码：华尔街报告披露，英伟达管理层表示 FY28 同比增长 70% 的目标并非需求上限——若供应不受限，增速可能超过 100%。当前主要约束已从需求端转向先进晶圆与 HBM 供应。

2. 单卡 2300W：风冷时代的终结​

Rubin 平台与前代最根本的差异不在算力，而在功耗密度：

指标	H100	GB300	Rubin
单 GPU TDP	700W	~1400W	2300W
机柜功耗	~40kW	~140kW	190–230kW
散热方案	风冷为主	风液混合	100% 全液冷
供电架构	48V	48V	800V 高压直流

单芯片 TDP 从 700W 升至 2300W、单机柜功率密度突破风冷物理极限——这意味着 液冷不再是高端算力的选配升级，而是运行 Rubin 服务器的先决条件。英伟达官方将 Rubin 全液冷架构定义为"数据中心历史上最重要的能效突破之一"，并已写入 DSX AI 工厂参考设计：所有跟随英伟达技术路线的云厂商和数据中心运营商，都必须采用全面液冷方案。

三个关键架构变化：

1. 无风扇整机：GPU、CPU、交换机、DPU 全部器件强制采用直接冷板式液冷，45℃ 温水冷板成为出厂标配；
2. 液冷边界延伸：散热覆盖范围从 GPU 冷板延伸至 CPU、DPU、交换机乃至光模块（液冷 Cage/鼠笼开始从"可选"变"刚需"），整套液冷系统价值量较 GB300 提升约 40%；
3. 800VDC 供电：替代传统 48V 机架配电，整机电源 BOM 价值增长 30% 以上，PSU 电源模块从 5.5kW 向 18.3kW 迭代，固态变压器、高压直流 CDU 成为数据中心新增核心设备。

3. 对产业链的三重传导​

第一重：液冷从"配套"变"主角"。 2026 下半年以小规模部署验证为主，真正的放量窗口在 2027 年——Rubin 机架大规模铺货后，冷板、快速接头、CDU、液冷泵进入业绩兑现期。台系供应链 7 月数据已率先验证：AVC 奇鋐 7 月营收 185.9 亿新台币创历史新高（同比 +57.4%），双鸿、健策 7 月同比分别 +116.7%、+91.0%。

第二重：国产液冷供应链进入核心 BOM。 国内厂商由外围冷源和代工环节逐步进入芯片平台、服务器 ODM 和海外云厂商供应体系，替代路径从 Manifold、管路推进至高可靠快接头和冷板。英维克 26H1 海外收入占比 71.4%，飞龙股份液冷泵小功率平台订单超 5 万台——液冷全核心零部件自主可控正在成为现实。

第三重：供电与散热边界融合。 800VDC 架构下，电源模块、PDB 配电单元、高速交换芯片自身发热也达到很高水平，部分电源组件同样需要液冷辅助散热——电源与温控两条产业链正在合并成一条。

4. 需求矩阵扩容：云厂商之外，太空算力入场​

Rubin 的客户矩阵已从传统云厂商扩展至三个层次：

• 全球云厂商：谷歌云、Azure、甲骨文云、CoreWeave；
• AI 科技巨头：马斯克公开披露 2027 年 8GW 超大规模 IDC 建设规划；SpaceX 将 Vera Rubin 架构定义为"最优 AI 计算架构"，计划地面与太空双向部署，支撑 "Starmind" 卫星算力项目；
• 主权与边缘：远期 Rubin Ultra 及 2027 年后更高功耗机型单机柜有望冲击 600kW+。

普华永道预计全球数据中心累计投资到 2035 年将达 31.6 万亿美元。AI 基础设施建设的确定性，已经从"是否建设"变成"多快建设"。

5. 对采购方的启示​

• 机房规划前置：2027 年起采购 Rubin 级算力，液冷改造（单千瓦改造成本较高）或按全液冷标准新建，必须在预算周期一开始就纳入；
• 看 PUE 也看水温：45℃ 温水直冷允许更高进水温度，可利用自然冷源压低 PUE——选址时人工冷源依赖度成为新的评估维度；
• 供应商组合即风险对冲：HBM 与先进封装供应是当前核心瓶颈（详见本站 HBM4 竞速分析），供应链多元化比单点性能更重要。

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相关链接​

• NVIDIA Rubin 规格页
• NVIDIA Rubin Ultra 规格页
• NVIDIA Rubin CPX 规格页

参考资料​

• 英伟达官方博客：Rubin 全液冷架构解析
• 财联社：Rubin 全面量产，看好液冷二次侧放量（2026-09-04）
• 东方财富研报：Vera Rubin 开启量产周期，AI 算力硬件环节迎来量价齐升（2026-08-27）
• 雪球：Vera Rubin 量产交付落地，全液冷 800V 高压架构重构（2026-09-03）

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本文基于 2026 年 9 月初供应链调研、券商研报与英伟达官方披露整理。出货量与功耗数据为产业链预估口径，实际以英伟达及客户正式披露为准。

August 23-25, 2026, the 38th Hot Chips (HC38) was held at Stanford's Memorial Auditorium. As the bellwether of global high-performance chip architecture, this conference landed exactly at the most intense moment of the AI compute arms race — the official agenda had 48 entries, including 7 AI accelerators, 6 memory tutorials, 6 CPUs, and 4 each of GPUs and networking. Putting the vendor talks together, one consensus emerged: the unit of AI compute competition has shifted from "single chip" to "whole rack / entire system."

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1. Overview: Three Days of Agenda, Almost a Preview of the 2027 AI Rack Market​

Monday (8/24) afternoon's GPU session was the focus, with four talks nearly colliding as the 2027 AI rack market:

• NVIDIA Rubin GPU ("Driving the Era of Agentic AI"): First chiplet-architecture GPU, 288GB HBM4, ~50 PFLOPS FP4, paired with 88-core Arm-architecture Vera CPU into NVL72 / NVL144 racks, mass production in H2 2026.
• AMD Instinct MI400 (two talks: architecture + system architecture): Told the "rack-scale" story thoroughly.
• Intel Crescent Island: A 350W air-cooled card designed for Agentic AI inference.

Tuesday (8/25) afternoon's AI session was almost a parade of "hyperscalers de-NVIDIA-izing": Google's 8th-gen TPU, OpenAI's first custom chip, Microsoft Maia 200, Meta MTIA, and Cerebras wafer-scale rack all appeared together.

Every vendor on stage used the term "Agentic AI" within the first two PPT slides — not a coincidence, but the collective shift in 2026 AI workload design goals.

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2. NVIDIA Rubin: One Rack Is a Supercomputer​

What NVIDIA featured at Hot Chips was not a single GPU but the Vera Rubin NVL72 whole cabinet — 72 Rubin GPUs + 36 Vera CPUs, 18 compute trays + 9 NVLink switch trays, about 1.3 million components, nearly 1,300 chips, weighing about 4,000 pounds (~1.8 tons).

The single Rubin GPU specs are equally stunning:

Metric	Rubin GPU	vs Blackwell
Transistors	336 billion (TSMC 3nm dual-die)	208 billion (+61.5%)
Memory	288GB HBM4	—
Bandwidth	22 TB/s	2.8× Blackwell
NVFP4 inference	50 PFLOPS	5× GB200
Training compute	35 PFLOPS	3.5×

The most disruptive design is in the compute tray: no cables, no hoses, no fans, all interconnected via the PCB backplane. NVIDIA says assembly time dropped from nearly 2 hours to 5 minutes (20× faster) while improving maintainability.

This time NVIDIA is selling not FLOPS but tokens per megawatt. Citing a SemiAnalysis benchmark based on DeepSeek-v4-PRO (140K+ context, AgentX workload), it claims: versus GB300 NVL72, Vera Rubin NVL72 delivers 10× to up to 30× tokens/MW as interaction intensity rises. A single cabinet provides 3.6 EFLOPS inference compute, whole-cabinet power 190-230kW; long-term capacity target is 1,000 NVL72 cabinets per day.

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3. AMD MI455X + Helios: Bigger Memory and Open Interconnect​

AMD's answer is the MI455X + Helios rack going head-to-head with NVIDIA. MI455X uses CDNA 5 architecture, 8 N2-process accelerator dies + N3P-process interconnect die, 256 workgroup processors, 192MB global L2.

Metric	MI455X	vs Rubin
Memory	432GB HBM4 (12-layer stack)	50% higher than Rubin's 288GB
Bandwidth	23.3 TB/s	Slightly ahead
MXFP4 compute	40.26 PFLOPS	—
System (Helios 72 cards)	2.9 ExaFLOPS FP4 inference	—
Price	~$5.25M per cabinet	—

At the system level, AMD bets on the UALoE (Ultra Accelerator Link over Ethernet) open standard: each GPU provides 3.6 TB/s bidirectional interconnect bandwidth; two 512-port 200G UALoE switch chips in the switch tray total 10.8 TB/s — opening the interconnect protocol to the whole industry while targeting NVLink.

Production cadence: AMD plans to deliver engineering samples and small-batch systems in H2 2026, with large-scale ramp in Q2 2027. Earlier rumors of Helios delay due to cooling issues were not confirmed by AMD.

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4. Intel Crescent Island: The Air-Cooled, Large-Memory "Cost-Effective Oddball"​

Intel offers a completely different path: Crescent Island — a 350W, air-cooled, standard-PCIe-slot inference GPU designed for Agentic AI, with the key metric being tokens per watt.

Metric	Crescent Island	Note
Architecture	Xe3P, 32 Xe cores, 32MB unified L2	Disclosed at Hot Chips
Memory	Intel branded card 160GB / ODM up to 480GB LPDDR5X	More than Rubin's 288GB HBM4
Form factor	350W air-cooled PCIe	Plugs into standard racks, no liquid-cooling retrofit
RAS	ECC, dynamic page offline, hard-package repair, PCIe advanced error reporting	Addresses "silent data corruption"

Intel's logic is clear: inference scenarios need far more memory capacity than bandwidth; using low-cost LPDDR5X for capacity and air cooling to skip liquid-cooling infrastructure drives down per-token cost. Combined with Diamond Rapids Xeon (256 performance cores, 1.28GB cache, 128 PCIe Gen6 lanes), Intel tries to surround from edge to datacenter with "CPU + inference GPU + open software stack."

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5. Custom ASIC Parade: Google, OpenAI, Microsoft, Meta Together​

Tuesday afternoon's AI session was the most historic of the conference — a parade of "hyperscalers de-NVIDIA-izing":

Chip	Vendor / Partner	Positioning	Key Specs / Progress
TPU 8t (Sunfish)	Google × Broadcom	Training	9,600 cards per pod, 121 FP4 ExaFLOPS, 2PB shared HBM
TPU 8i (Zebrafish)	Google × MediaTek	Inference	288GB HBM, 384MB on-chip SRAM (3× prev gen), ICI 19.2 Tb/s
Jalapeño	OpenAI × Broadcom	Inference	9-month end-to-end design, target ~50% token cost cut, commercial end of 2026
Maia 200	Microsoft (TSMC 3nm)	Inference	140B+ transistors, 10+ PFLOPS FP4, 216GB HBM3E, serving GPT-5.2 at Des Moines datacenter
MTIA 300-500	Meta (RISC-V) × Broadcom	Training + inference	Up to 25× compute gain, one model every 6 months before 2027

Google split TPU into training (8t) and inference (8i) dedicated architectures for the first time — its biggest architectural shift in a decade. Norm Jouppi personally took the stage to present TPU v8.

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6. Two Hidden Threads — Memory and Networking: HBM4 Year 1 + AI Factory OS​

Beyond GPUs/ASICs, two hidden threads mattered equally:

• Memory: Samsung's HBM Base Die (logic-process base die) and SK hynix's advanced packaging appeared together; the HBM4-era "base-die foundry" industry shift begins; HBF (high-bandwidth flash), LPDDR5X-PIM, 3D DRAM, and CXL compute-storage showcased "compute-in-memory" moving from papers to products.
• Networking: NVIDIA BlueField-4 (DPU) and Spectrum-X Multiplane architecture (presented by Gilad Shainer) — networking is becoming the decisive architecture for gigascale AI, scaling from hundreds of thousands to a million cards; Broadcom Thor Ultra Ethernet NIC keeps pressing; Mojo Vision showed chip-level optical I/O.

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7. Three Routes, One Consensus​

At the same conference, three vendors offered three distinctly different AI compute delivery philosophies:

1. NVIDIA: Full-stack closed integration — GPU, CPU, DPU, and switch chips all self-designed, pushing system performance to the extreme via ultimate software-hardware co-design, at the cost of deep customer lock-in.
2. AMD: Open-standard catch-up — Uses larger HBM4 capacity + UALoE open interconnect for a "cost-effective + open" play, tearing open the inference gap with Meta and OpenAI's 12GW-class orders.
3. Intel: Air-cooled cost-effectiveness — Abandons liquid cooling and HBM, uses LPDDR5X large memory + standard PCIe, betting that "most inference doesn't need a 200kW rack."

But all three agree: the unit of competition is no longer the chip, but the co-designed system (rack / system). For buyers, 2027 compute planning should compare not "single-card PFLOPS" but "tokens per megawatt, latency, availability, and full-lifecycle cost."

Related Links​

• NVIDIA Rubin spec page
• AMD MI455X spec page
• Intel Crescent Island spec page
• Google TPU 8t spec page
• Google TPU 8i spec page

References​

• Hot Chips 2026 Three Giants Together: Rubin 336B Transistors, MI455X 432GB, Crescent Island 480GB - IC Chip Industry Watch
• Hot Chips Day 2: Rubin, MI400 and Diamond Rapids Go Head-to-Head - AI2Work
• NVIDIA Vera Rubin NVL72 Rack at Hot Chips 2026 - ServeTheHome
• Hot Chips 2026: 4 Hyperscalers Put Custom AI Silicon on One Afternoon - Sean Kim

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This article is compiled from Hot Chips 2026 (Aug 23-25) official presentations and on-site reports from ServeTheHome, SemiAnalysis, TechPowerUp, etc. Performance data are vendor-disclosed figures; actual performance subject to mass-produced products.

If 2025 was the year of HBM3E capacity ramp-up, then 2026 is year one of HBM4 mass production. With NVIDIA Vera Rubin and AMD MI400 — two generations of flagship — both betting on HBM4, this "memory on the AI chip" has for the first time become a strategic commodity that dictates the delivery pace of entire racks. The yield and certification data disclosed densely in August is rewriting the global HBM supply map.

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1. Golden Yield Breakthrough: Samsung Jumps from Under 60% to 80% in Six Months​

Per South Korea's Seoul Economic Daily on August 9, Samsung Electronics' HBM4 yield officially crossed the 80% "golden yield" threshold in early August — more than four months ahead of its original year-end target.

Timeline	Samsung HBM4 Yield	Notes
Feb 2026 (mass production start)	Under 60%	Line ramp-up period
Early Aug 2026	~80%	Crosses the mass-production / stable-profit watershed

The semiconductor industry has long held that "80% yield is the golden yield" — it is both a yardstick of foundry competitiveness and the financial break-even point for large-scale commercial supply. The key to this leap was Samsung's breakthrough in Thermal Compression Non-Conductive Film (TC-NCF) bonding, plus the stable base of its underlying 1c DRAM yield, already above 80%. In the same period, Samsung's HBM4E reliability test yield also broke 70%.

Industry assessments suggest SK Hynix's HBM4 yield has likewise entered the 80% range. The gap between the two giants in production quality is being rapidly erased.

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2. Supply Map: SK Hynix Holds 60–70% of Rubin Allocation​

At a Seoul event on June 5, Jensen Huang publicly confirmed: Samsung, SK Hynix, and Micron have all passed HBM4 certification for Vera Rubin — the first time three memory makers have simultaneously received public certification for the same platform.

But certification is just the "entry ticket" — allocation share is where the real voice lies:

Vendor	2026 Rubin HBM4 Allocation (est.)	Notes
SK Hynix	60%–70%	Based on HBM3/3E-era customer relationships and MR-MUF packaging
Samsung	25%–30%	Rapid share gains after yield leap
Micron	Remainder	Limited HBM4 exposure, relatively stable share

Counterpoint Research forecasts the 2026 HBM4 market as SK Hynix 54% / Samsung 28% / Micron 18%. Samsung has set staged catch-up targets: Q3 HBM4 revenue up 3× QoQ, HBM4 exceeding 60% of total HBM revenue in H2, and year-end overall HBM market share approaching 38%.

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3. The Real Bottleneck: From Wafers to "Back-End Stacking"​

As front-end yield stabilizes, the rhythm of the AI accelerator supply chain no longer depends on "how many wafers can be made," but on the speed of back-end stacking, bonding, testing, and shipment.

• Industry analysts rank HBM stacking as the second-most severe bottleneck in the AI chip supply chain, second only to TSMC's CoWoS advanced packaging capacity.
• HBM accounts for roughly 25% of 2026 DRAM wafer output; each HBM wafer consumes about 3–4× the resources of a standard DRAM wafer (extra TSV and stacking steps), so every wafer redirected pulls 3–4 units of commodity memory off the spot market.
• Samsung is considering relocating part of its legacy memory back-end lines (Cheonan, Onyang) to Vietnam to free up HBM back-end capacity — a side confirmation that back-end throughput is now the tightest link in the chain.

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4. HBM4 Spec Snapshot: Generational Leap in Bandwidth and Efficiency​

Spec	HBM4 (12-Hi / 16-Hi)	HBM4E
Per-stack capacity	36 GB / 48 GB	—
Pin rate	11.7–13.0 Gbps	16 Gbps
Per-stack bandwidth	up to 3.3 TB/s	up to 3.6 TB/s
Bus width	2048-bit	—
Energy efficiency	+40% vs HBM3E	—
Thermal resistance / cooling	+10% improvement / +30%	—

Samsung HBM4 entered mass production in Feb 2026; its 11.7 Gbps pin rate already exceeds the 8 Gbps industry baseline required for Vera Rubin compatibility; HBM4E samples were first shipped to major customers on May 29.

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5. Pricing Power Extends Into 2027: Supply Remains Tight Balance​

TrendForce judges that HBM suppliers' pricing power will run through 2027, because supply remains constrained:

• 2027 HBM bit shipments are expected to grow 50%–60% YoY, but will still lag demand growth, keeping the market tight;
• The industry already anticipates significant price increases;
• For NVIDIA and AMD, a stronger Samsung means more supply options and more comfortable lead times — in a market where memory is the tightest link in AI servers, the mere existence of second and third suppliers is itself a buffer.

For entire racks, HBM cost is already the biggest driver: the Rubin Ultra rack carries an estimated price tag as high as $21 million, with HBM making up a substantial portion.

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6. Lessons for China: HBM Export Controls Accelerate Domestic Iteration​

HBM is one of the core fronts of current AI chip controls. As the overseas HBM4 arms race intensifies, domestic HBM technology iteration is being pushed forward in sync — Huawei's Ascend roadmap has explicitly written "drive domestic HBM technology iteration" into its product cadence (the 950 series advances domestic HBM pairing, with the 960/970 series planned for gradual rollout in 2027–2028).

In the short term, HBM4 scarcity will directly transmit to the delivery cadence of Rubin / MI400; in the long term, whoever can lock in stable HBM4 supply holds the valve on 2027 AI compute expansion.

Related Links​

• NVIDIA Rubin Spec Page
• AMD MI455X Spec Page
• Hot Chips 2026 Full Recap

References​

• Samsung's HBM4 Yield Hits 80% as HBM Race Heats Up - TrendForce
• Samsung HBM4 Yield Hits 80%, Boosting AI Memory Supply - PC Central
• Samsung Weighs Shipping Legacy Memory Backend to Vietnam to Unlock HBM Capacity - TechTimes
• 芯闻|六个月良率跃迁：三星HBM4突破80%黄金门槛 - Toutiao

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This article is compiled from August 2026 public reports by TrendForce, Seoul Economic Daily, TechTimes, etc. HBM allocation shares and market shares are third-party estimates, not official vendor-confirmed data.

July 2026, NVIDIA's next-gen AI compute platform Vera Rubin officially began its first shipments, succeeding the Blackwell architecture, with large-scale mass production planned for H2 2026. First customers include Microsoft, Google, Amazon, Meta, Oracle, and other large cloud providers.

1. World's First VR200 NVL72 Delivered (Milestone)​

CoreWeave jointly with Dell announced that the world's first NVIDIA Vera Rubin VR200 NVL72 cabinet has been officially delivered and passed the L11 full-cabinet hardware diagnostics on the first try. This marks Rubin's move from roadmap to physical product, with no major bottlenecks in core supply-chain links (HBM4, advanced packaging, liquid cooling, ultra-high-power power supply).

VR200 NVL72 Core Configuration​

Metric	Vera Rubin VR200 NVL72
Cabinet codename	Oberon
GPU	72 Rubin GPUs
CPU	36 Vera CPUs
Per-GPU memory	288 GB HBM4
Per-CPU memory	1.5 TB LPDDR5X
Total cabinet HBM4	20.7 TB (20,736 GB)
Total cabinet LPDDR5X	54 TB
Interconnect	NVLink 6 full mesh
Inference performance	~3.6 exaFLOPS class
Cooling	Liquid cooling
Generational improvement	~3.5× per-GPU compute, ~2.8× memory bandwidth (vs Blackwell)

Vera CPU integrates 88 custom Olympus ARM cores, with 1.8 TB/s interconnect to the GPU, usable as a GPU memory expansion pool. NVIDIA completed its first Vera CPU deliveries to Anthropic, OpenAI, xAI, and Oracle Cloud in May.

2. Samsung HBM4 Mass Production: Key Bottleneck Eases​

July 8, 2026, Samsung Electronics officially started HBM4 mass production for the Vera Rubin platform, with reported HBM4 mass-production yield reaching 70% (above the initial 60-65% expectation). Confirmation of this key supply-chain link clears obstacles for Rubin's large-scale deployment.

HBM Supply Landscape (2026 Q1)	Share
SK hynix	45%
Samsung	40%
Micron	15%

HBM4 uses 8-layer stacking (12-layer design planned for 2028), priced at about 2.8× HBM3e. TrendForce predicts HBM supply will grow 65% annually, with HBM4 reaching 35% of total output by 2027 Q4.

3. Rubin Ultra Sky-High Price: HBM Cost Dominates​

Per BofA Global Research estimates, the Rubin generation will push single-server cost to a new high:

Cost Item	Rubin VR200 (Oberon)	Comparison
Cabinet HBM4 usage	20,736 GB	—
HBM4 unit price	~$18.40 / GB	Blackwell (HBM3e) ~$11.26 / GB
HBM4 cost alone	~$382K	Excluding LPDDR5X
Rubin Ultra cabinet estimated price	~$21M	ITHome / BofA estimate

4. Rubin Ultra Design Change: Original 4-die Cancelled (per SemiAnalysis)​

Semiconductor research firm SemiAnalysis (2026-06-30) disclosed that the original 4-die Rubin Ultra GPU unveiled at GTC 2026 has been cancelled; the version actually shipping in 2027 is roughly halved in scale and performance:

• Reason for cancellation: The original integrated 4 compute dies + 16 HBM4E in a single CoWoS-L package; the substrate warped under the 4-die config, causing compute-die-to-substrate contact failure and yield collapse; the alternative CoPoS won't reach mass production until after late 2028, missing the 2027 node.
• New approach: Changed to dual-die (same construction as standard Rubin) + HBM4E, ~384 GB HBM4E per GPU (higher than standard Rubin's 288 GB), but total compute and bandwidth only half the original; to approach the original's aggregate compute, NVIDIA plans to assemble "2+2" board-level configs within the Kyber rack to reach four-die equivalent scale.
• Kyber rack delay: The companion Kyber NVL144 rack is delayed 12+ months to 2028 due to midplane PCB manufacturing difficulties; the 800V DC power scheme is likewise delayed to 2028.

⚠️ Note: NVIDIA has not commented officially on the above design change; some on X argue "the chip count hasn't changed, it's old news reheated." This section is compiled from SemiAnalysis public reports, subject to final NVIDIA disclosure. We have marked "specs pending official confirmation" on the Rubin Ultra preview card.

Industry Interpretation​

1. "Never doubt" moment realized: Rubin's first delivery passed L11 on the first try, dispelling market doubts about "Rubin delay," locking in H2 2026 AI compute supply certainty ahead of time.
2. Designed for Agentic AI: Rubin targets agentic workflows and ultra-long-context inference, further lowering the training/inference cost curve for trillion-parameter models.
3. HBM is the full-chain winner: 20.7 TB HBM4 per cabinet is enormous usage; SK hynix, Samsung, Micron, advanced packaging (CoWoS-L), liquid cooling, and power retrofitting all benefit across the chain, while also becoming the biggest cost and capacity constraint.

Related Links​

• NVIDIA Rubin R200 spec page
• NVIDIA Vera CPU spec page
• NVIDIA Rubin CPX spec page

References​

• Samsung Starts Mass Production for Nvidia's Vera Rubin AI Platform (2026-07-08)
• Rubin cabinet first delivery: CoreWeave and Dell deliver world's first VR200 NVL72
• Nvidia Rubin Ultra cabinet estimated at $21M - ITHome (2026-07-09)
• NVIDIA Vera Rubin scheduled for July 2026 shipment - VendorDeep

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This article continuously tracks Vera Rubin mass-production ramp and HBM4 supply-chain dynamics.

In the first half of 2026, the AI chip industry underwent a historic turning point — the center of gravity shifted from the "training race" to "inference efficiency," domestic chip market share broke 40% for the first time, NVIDIA built higher barriers with Blackwell Ultra, and the inference-specific chip track bloomed in diversity.

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I. Compute Doubles Again: NVIDIA Blackwell Ultra Launch (June 1)​

On June 1, 2026, NVIDIA CEO Jensen Huang unveiled the new-generation AI chip Blackwell Ultra at Computex 2026 (Taipei), setting a new starting line for the AI infrastructure race over the next two years.

Key Specs​

Metric	Blackwell Ultra	B200	Improvement
FP8 compute	20 petaFLOPS	~10 petaFLOPS	100%
Architecture	Blackwell Ultra	Blackwell	Upgrade
Expected delivery	2027 Q1	2026 Q1	—
Positioning	Hyperscale training + inference	Training + inference	Flagship

Industry Significance​

1. Direct impact of doubled compute: 20 petaFLOPS FP8 means training time for hundred-billion-parameter models drops sharply; trillion-parameter model training moves from "scientific experiment" to "engineering routine"
2. System-level balance: Blackwell Ultra is not just a chip but a system-level engineering breakthrough across NVLink, HBM, cooling, and power delivery
3. Roadmap certainty: The Q1 2027 delivery timeline lets cloud vendors and AI labs plan infrastructure budgets 18 months ahead

Challenges​

• Energy crisis: Doubled performance comes with sharply higher power; datacenter power and cooling design face extreme challenges
• Accessibility: Top-tier compute goes first to top cloud vendors; how smaller developers and research institutes reach compute at reasonable cost via cloud services
• Software stack adaptation: New hardware needs matching CUDA versions and framework support; software ecosystem maturity becomes the key bottleneck for compute conversion

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II. Domestic AI Chips: The Tipping Point from "Usable" to "Good"​

On June 16, 2026, Xinchuang World published "2026 China Domestic AI Chip Vendor Capability Quadrant", clearly outlining the overall domestic landscape.

2.1 Capability Quadrant Ranking​

Quadrant	Representative Vendors
Leader quadrant	Huawei Ascend, Hygon, Cambricon, Alibaba T-Head, Moore Threads
Visionary quadrant	Baidu Kunlunxin, Biren, Enflame, Iluvatar, HardyVision
Contender quadrant	TSINGMICRO, Black Sesame, SemiDrive, Lisuan, Houmo
Challenger quadrant	Denglin, Zhicun, VeriSilicon, Rockchip, Intellifusion

2.2 Huawei Ascend: The Anchor of Domestic Compute​

Market Position​

• In 2025, Ascend series shipped 812,000 units, capturing 49% of the domestic AI accelerator card share, firmly No.1 domestically
• Ascend 950PR single-card FP8 compute reaches 1P (PetaFLOPS), FP4 compute reaches 2P
• Inference performance is about 2.87x that of NVIDIA H20, priced at only 72,000-75,000 RMB, a significant price/performance advantage

Full-Stack Advantage​

Huawei's "device-network-cloud-chip" integrated strategy is Ascend's core moat:

• Chip design: Da Vinci 3.0 architecture iterating continuously
• OS: HarmonyOS/Euler OS deeply optimized
• Networking: Euler network protocol stack
• Cloud: Huawei Cloud ModelArts platform seamlessly integrated

Latest Progress​

• On June 5, 2026, Shenzhen Hetao College, together with HIT (Shenzhen) and Huawei, completed full-parameter post-training of a 1.6-trillion-parameter DeepSeek V4 Pro model on an Ascend 910C cluster
• This is the first time domestic AI chips completed trillion-parameter-level model training, marking "domestic substitution" moving from inference to training

2.3 Cambricon: The First Profitable Domestic AI Chip Benchmark​

Performance Explosion​

Metric	Full-year 2025	2026 Q1	YoY Growth
Revenue	6.497B RMB	2.885B RMB	+453% / +160%
Net profit	2.059B RMB (first annual profit)	1.013B RMB	— / +185%

Core Product: Siyuan 590​

• In DeepSeek R1 inference scenarios, TPS reaches 942, about 50% higher than H20
• Years of joint optimization with ByteDance; strongest short-term cloud inference deployment capability
• Of 2.885B RMB Q1 2026 revenue, Siyuan 590 contributed over 70%

Potential Risks​

Absent from the 2nd 2026 "Safe and Reliable Evaluation Results Announcement"; the reason is unclear and will affect its domestic government/enterprise market performance.

2.4 TSINGMICRO: The "Third Route" of Reconfigurable Chips​

Technical Route​

TSINGMICRO adopts a reconfigurable dataflow architecture同源 with Groq LPU, finding a balance between GPU generality and ASIC extreme efficiency.

Metric	TSINGMICRO TX81	Traditional GPU	Advantage
Inference cost	Baseline	+100%	Reduced 50%
Energy efficiency	Baseline	Baseline	3x improvement
Architecture	Reconfigurable dataflow	SIMT/SIMD	Better for inference

Deployment Progress​

• Cumulative shipments of reconfigurable chips exceed 30 million units
• Scaled deployment in a dozen-plus thousand-card-scale intelligent computing centers nationwide
• Has begun A-share IPO tutoring; likely to become the "first reconfigurable chip stock"

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III. The Inference Chip Track: Core Signal of the Industry Shift​

On June 4, 2026, TrendForce published a deep report "The Era of Inference Economy: The Rules of AI Chips Are Being Rewritten," pointing out that the compute competition center of gravity is shifting from training to inference.

3.1 Why Now?​

Cost Structure Changed​

• Training is a one-time cost: Once a model is trained, marginal cost approaches zero
• Inference is a recurring cost: Every API call, every generated token represents compute consumption and gross-margin pressure
• Per-unit inference cost and energy efficiency directly affect gross margin and scale-expansion capability

Model Compression Tech Matured​

• 1.58-bit quantization and weight pruning let models maintain inference accuracy at extremely low memory footprint
• MoE (Mixture of Experts) architecture activates only a few expert sub-networks per inference via "partial wake-up," greatly reducing actual computation
• The rise of slimmed models provides commercial viability for hard-wired inference chips

3.2 NVIDIA's $20B Bet: Acquiring Groq (December 2025)​

On December 24, 2025, NVIDIA acquired Groq's inference technology license and core team for $20 billion, one of NVIDIA's largest M&A/tech acquisitions ever.

Strategic intent:

1. Fill the inference gap: NVIDIA GPU is unshakable in training, but inference efficiency was never its strongest suit
2. Counter specialized inference chips: Cerebras, Taalas, SambaNova and other startups are eroding the inference market
3. Position for Agentic AI: Agentic AI needs extremely low-latency, high-throughput inference

3.3 Taalas HC1: Proof of Concept for Hard-Wired Inference​

On February 20, 2026, Canadian AI chip startup Taalas launched inference chip Taalas HC1, directly etching Meta's open-source AI model Llama 3.1 8B into the chip.

Key Metrics​

Metric	Taalas HC1	NVIDIA B200 (throughput optimized)	Advantage
Inference rate	16,960 tokens/s/user	Baseline	~4-5x
Cost per million tokens	0.75 cents	3.79 cents	Reduced 80%
Power	~250W	~700W	Reduced 64%
Process	TSMC N6	TSMC 4nm	More mature
HBM	❌ Not used	✅ HBM3e	Lower cost

Technical Principle​

Taalas HC1 uses an aggressive Computing-in-Memory (CIM) implementation:

• Model weights directly固化 in Mask ROM (fully hardware-defined)
• On-chip SRAM handles dynamic data (KV cache and LoRA fine-tuning weights)
• Only 2 mask layers need modification to produce a dedicated chip for another AI model; turning an AI model into a physical chip takes only 2 months

Limitations​

• Lack of flexibility: Hard-wiring cannot cope with rapidly iterating model updates
• Ecosystem barrier: The current cloud market still relies on general-purpose platforms; customers may prefer flexible solutions that upgrade with models
• NRE cost: High one-time engineering cost, requiring sufficient deployment scale to amortize

3.4 Cerebras: The IPO Path of Wafer-Scale Integration​

On May 14, 2026, Cerebras Systems officially listed on NASDAQ, becoming the first wafer-scale AI chip company to go public.

Core Technology: Wafer-Scale Integration (WSI)​

• WSE-3 (third-gen wafer-scale engine): An entire 12-inch wafer as a single chip
• 44GB on-chip SRAM: No external HBM, eliminating the memory bandwidth bottleneck
• 21 PB/s bandwidth: On-chip communication bandwidth, thousands of times that of GPUs
• Partnership with OpenAI: Signed a 3-year, 750MW, $20B+ compute cooperation agreement

IPO Significance​

Cerebras's listing marks the maturation of the inference-specific chip track:

1. Capital markets begin pricing such companies
2. Proves "non-GPU" technical routes have commercial viability
3. Provides valuation references for other inference chip startups (Groq, SambaNova, Taalas, etc.)

3.5 Inference Chip Landscape: Multiple Technical Routes Coexist​

Company	Technical Route	Core Advantage	Representative Product
Taalas	Hard-wired (Mask ROM)	Extreme inference efficiency, low cost	HC1
Cerebras	Wafer-scale integration (WSI)	Ultra-high bandwidth, large-model inference	WSE-3
Groq	SRAM-first architecture	Deterministic latency, high throughput	LPU (acquired by NVIDIA)
d-Matrix	Digital in-memory compute (DIMC)	More flexible than hard-wiring	Corsair
Etched	Hard-wired Transformer	Works for all Transformer models	Sohu
Axelera AI	Digital in-memory compute (D-IMC) + RISC-V	High energy efficiency	Metis AIPU

TrendForce predicts:

• General-purpose GPUs still dominate training and multi-model environments
• But in mature, predictable scenarios, general-purpose GPU profit margins will be compressed
• The industry shifts from general compute monopoly to a dual-track structure of general + specialized coexistence

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IV. Overall Domestic AI Chip Landscape in H1 2026​

4.1 Industry Enters Scale-Up Phase​

Metric	2025	2026 Q1	Trend
Domestic AI accelerator shipments	1.65M units (41% share)	—	Rising
Total China AI accelerator shipments	~4M units	—	—
Hygon revenue growth	—	Doubled	↑
Cambricon revenue growth	—	+160%	↑
Moore Threads revenue growth	—	Doubled	↑

Leading vendors collectively entered the revenue realization channel, moving from "technical validation" to "scale commercialization."

4.2 Three Core Development Trends​

Trend 1: Capitalization Wave Reshapes the Landscape​

• Late 2025 to early 2026: Moore Threads, Iluvatar listed on the STAR Market
• Biren listed on the Hong Kong stock exchange
• Enflame STAR Market IPO accepted
• Kunlunxin, T-Head initiated listing processes
• TSINGMICRO, HardyVision and others advancing IPOs

Capitalization brings dual effects:

• ✅ Positive: Supports R&D and ecosystem building
• ⚠️ Negative: Valuation bubbles and revenue realization pressure

Trend 2: Capacity Becomes the Biggest Constraint Variable​

The contradiction between explosive domestic AI chip demand and limited advanced-process capacity is sharpening:

Vendor	Advanced-process capacity need	Actually obtained
Huawei Ascend	15K wafers/month (7nm-class)	Priority guaranteed
SMIC total capacity	~20K wafers/month (7nm-class)	—
Other vendors	~5K wafers/month combined	Extremely tight

Whether stable wafer capacity can be secured directly determines vendor survival. Cambricon's 75.4% inventory-to-revenue ratio is essentially a lock on capacity.

Trend 3: Competition Shifts from "Usable" to "Good"​

Early competition focused on "can it run the model"; now it's about "runtime efficiency, deployment cost":

Dimension	"Usable" era	"Good" era
Hardware performance	Can it run the model	Runtime efficiency, energy efficiency
Software stack	Basic adaptation	Maturity, framework breadth
Ecosystem	Existence	Developer community activity
Deployment cost	Insensitive	Core competitive factor

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V. H2 2026 Outlook​

5.1 Upcoming Key Events​

Time	Event	Impact
2026 Q3	NVIDIA Rubin architecture details revealed	Next-gen flagship specs unveiled
2026 Q3	Huawei Ascend 950PR/950DT formally launched	New benchmark for domestic inference chips
2026 Q4	AMD MI350X scaled delivery	NVIDIA Blackwell competitor
2026 Q4	Cambricon Siyuan 690 launch (est.)	New-gen training chip
2027 Q1	NVIDIA Blackwell Ultra delivery	New compute benchmark lands

5.2 Key Competitive Factors Over the Next Three Years​

1. Wafer capacity access: Advanced-process capacity is a scarce resource; vendors tied to SMIC and TSMC have inherent advantages
2. Capital operation efficiency: The IPO window is limited; raising enough capital on the market determines R&D sustainability
3. Software ecosystem depth: Hardware performance is only the entry ticket; software stack maturity, framework adaptation breadth, and developer community activity are the core moat

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VI. Conclusion: A Diverse Ecosystem Will Eventually Form​

In H1 2026, the AI chip industry is undergoing a historic transition from "one dominant player" to "pluralistic coexistence."

• NVIDIA builds higher training barriers with Blackwell Ultra while laying out inference efficiency via the Groq acquisition
• Huawei Ascend holds the domestic compute baseline with full-stack capability; 950PR begins to surpass H20 in inference
• Cambricon proves the commercial viability of domestic AI chips by turning profitable first; Siyuan 590 surpasses international rivals in specific scenarios
• Cerebras, Taalas and other inference-specific chip companies opened a "non-GPU" third route
• TSINGMICRO's reconfigurable architecture provides a diversified technical route choice for China's AI chips

Over the next three years, the domestic AI chip endgame will form a pluralistic ecosystem where GPU, ASIC, and reconfigurable computing three technical routes coexist, with cloud and edge developing in coordination. "Domestic substitution" is no longer a slogan, but an industrial reality happening now.

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Data sources:

• Xinchuang World "2026 China Domestic AI Chip Vendor Capability Quadrant" (2026-06-16)
• TrendForce "The Era of Inference Economy: The Rules of AI Chips Are Being Rewritten" (2026-06-04)
• RayByte "Compute Doubles! NVIDIA Blackwell Ultra Chip Launched" (2026-06-02)
• Official financial reports and announcements of each company

Related reading:

• Huawei Ascend 910C Specs Deep Dive
• Full Comparison Table

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