14 posts tagged with "Huawei"

June 2026 saw multiple milestone events in the AI chip field, marking acceleration of two major trends: "domestic substitution" and "de-NVIDIA-ization."

1. Huawei Ascend 910C Completes 1.6-Trillion-Parameter DeepSeek V4 Pro Training (2026-06-05)​

Event Overview​

June 5, 2026, Shenzhen Hetao College, together with Harbin Institute of Technology (Shenzhen), Shenzhen Big Data Research Institute, Huawei, and other teams, relied on an Ascend 910C domestic AI compute cluster to successfully complete full-parameter post-training of the 1.6-trillion-parameter DeepSeek V4 Pro large model.

Technical Significance​

Metric	Value
Model parameters	1.6 trillion
Training chip	Ascend 910C cluster
Training type	Full Parameter Post-Training
Significance	First time domestic AI chips complete trillion-parameter-level model training

Industry Impact​

1. Breaks technology blockade: Proves domestic AI chips can train trillion-parameter models
2. Accelerates "farewell to NVIDIA": DeepSeek fully switches to Huawei Ascend, reducing dependence on H100
3. Domestic substitution inflection point: From "inference substitution" to "training substitution"

Related Links​

• Huawei Ascend 910C spec page
• DeepSeek V4 Pro official announcement (pending)

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2. OpenAI Launches First Custom AI Inference Chip Jalapeño (2026-06-24)​

Event Overview​

June 24, 2026, OpenAI and Broadcom jointly launched the first custom AI inference chip Jalapeño, with a design cycle of only 9 months (industry average 18 months), using TSMC 3nm process.

Key Metrics​

Metric	Jalapeño	Comparison (Blackwell)
Process	TSMC 3nm	TSMC 4nm
Architecture	Systolic Array	Blackwell GPU
Design cycle	9 months	~18 months
Inference cost	-50%	Baseline
AI-assisted design	✅ First	❌ No
Deployment	End of 2026	Shipped

Strategic Significance​

1. First AI chip with AI-assisted design: OpenAI used models like GPT-5.3-Codex-Spark to assist architecture exploration
2. Accelerates "de-NVIDIA-ization": Tech giants (Google, Amazon, Microsoft, Meta, OpenAI) collectively develop custom chips
3. Inference cost revolution: For OpenAI processing hundreds of millions of API calls daily, a 50% cost reduction is significant

Related Links​

• OpenAI Jalapeño spec page
• OpenAI Custom Chip Deep Dive

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3. NVIDIA Launches RTX Spark AI PC Superchip at Computex 2026 (2026-06-01)​

Event Overview​

June 1, 2026, NVIDIA CEO Jensen Huang launched the RTX Spark AI PC superchip at Computex 2026 / GTC Taipei, in collaboration with MediaTek, using an Arm CPU + Blackwell GPU unified-memory architecture.

Key Metrics​

Metric	RTX Spark
CPU	Up to 20-core Arm (with MediaTek)
GPU	6,144 CUDA cores (Blackwell)
Unified memory	128GB LPDDR5X (shared CPU+GPU)
Memory bandwidth	300 GB/s
AI compute	~1 PFLOPS (est.)
Model capacity	Can run 120B-parameter models
Context	Up to 1 million tokens
TDP	~100W (est.)
Availability	Fall 2026

Industry Impact​

1. NVIDIA enters PC chip market: Challenges Intel's dominance in personal computers
2. New AI PC standard: Run 120B-parameter models locally, 1M-token context
3. Windows transforms into AI Agent platform: Deep collaboration with Microsoft OpenShell framework

Related Links​

• NVIDIA RTX Spark spec page
• Computex 2026 Chip War Deep Dive (external link)

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4. MIIT Publishes "2026 AI Chip Industry Development White Paper" (2026-06-09)​

Event Overview​

June 9, 2026, China's Ministry of Industry and Information Technology published the "2026 AI Chip Industry Development White Paper," predicting the domestic AI chip market will exceed 200 billion RMB in 2026.

Key Predictions​

Metric	2026 Prediction
Market size	Exceed 200 billion RMB
Domestic chip share	>50% (41% in 2025)
Edge inference chips	Significant progress
Shipment growth	More than double (vs 2025)

Industry Significance​

1. Domestic AI chip capitalization accelerates: Cambricon, Enflame, Moore Threads, etc. accelerate IPOs
2. Edge inference becomes the breakthrough: Easier to achieve domestic substitution than training chips
3. Policy dividend continues: Domestic substitution upgraded from "market behavior" to "national strategy"

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5. ByteDance in Talks to Procure 50K Iluvatar Inference Chips (2026-06-17)​

Event Overview​

June 17, 2026, Reuters reported that ByteDance is in talks with Shanghai AI chip firm Iluvatar to procure at least 50,000 AI chips, mainly for inference tasks.

Deal Details​

Item	Content
Buyer	ByteDance
Supplier	Iluvatar
Chip model	ZhiKai series (inference GPU)
Quantity	At least 50,000
Use	Inference workloads
Training chip	TianTai series

Industry Significance​

1. Domestic GPU top player "adds a member": Iluvatar enters a top internet company's supply chain for the first time
2. ByteDance 2026 capex raised over 200B RMB: Mainly for AI compute and datacenters
3. "Domestic substitution" extends from government/SOEs to private tech giants

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Summary: Three Trends in June 2026 AI Chip Industry​

Trend 1: "Domestic Substitution" Moves from Inference to Training​

• Ascend 910C completes 1.6-trillion-parameter model training → Proves domestic chips have training capability
• DeepSeek fully switches to Ascend → Leading AI companies first to "farewell to NVIDIA"
• ByteDance procures Iluvatar → Private tech giants follow

Trend 2: "De-NVIDIA-ization" from Slogan to Action​

• OpenAI Jalapeño → First custom chip, inference cost -50%
• Google TPU, Amazon Trainium, Microsoft Maia → Continuous iteration
• Meta MTIA, Apple M5 Ultra → Increased investment

Trend 3: AI PC and Edge Inference Become New Battlefield​

• NVIDIA RTX Spark → New AI PC standard, launches Fall 2026
• Edge inference chip localization accelerates → Key mention in MIIT white paper
• "Local trillion-parameter model execution" → New consumer market selling point

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Looking Ahead (2026 H2)​

1. Ascend 950DT full scale-up (2026 Q4) → Huawei's latest-gen training chip
2. NVIDIA Rubin R200 shipment (2026 H2) → Next-gen flagship
3. AMD MI400 Helios rack (2026 H2) → Targets NVIDIA GB200
4. OpenAI Jalapeño deployment (end of 2026) → Gigawatt-scale datacenters
5. Domestic AI chip shipments more than double → CITIC Securities prediction

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References​

• Huawei Ascend 910C Completes DeepSeek V4 Pro Training - Tencent News
• OpenAI Jalapeño Chip Launch - CNBC
• NVIDIA RTX Spark Launch - Tencent News
• MIIT AI Chip White Paper - RayByte
• ByteDance Procures Iluvatar Chips - Sina Finance

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This article is continuously updated. Please provide the latest developments.

Against the backdrop of U.S. export controls, China's AI chip market is forming a "three-way standoff." This article compares the technical routes, product specs, software ecosystems, and commercial progress of the three major domestic AI chip vendors: Huawei Ascend, Cambricon MLU, and Moore Threads MTT.

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Key Points​

• Huawei Ascend: leader in domestic AI training chips; Ascend 950 in mass production; most mature software ecosystem
• Cambricon MLU690: the "China H100," compute close to H200, clear efficiency advantage
• Moore Threads MTT S5000: full-function GPU route; achieved Day-0 support for Qwen3.5 and GLM-5.2 in June 2026
• Shared challenge: affected by U.S. export controls, primarily aimed at the Chinese market, limited internationally

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I. Vendor Overview​

Vendor	Founded	Founder	Listed	2025 Revenue	Main Customers
Huawei Ascend	2018 (division)	Ren Zhengfei	private (wholly owned by Huawei)	~¥20B (est.)	Chinese gov, SOEs, military
Cambricon	2016	Chen Tianshi (CAS)	2020-07 (STAR Market 688256)	~¥5.2B	ByteDance, Alibaba, Baidu
Moore Threads	2020	Zhang Jianzhong (ex-NVIDIA China)	2023-12 (STAR Market 688495)	~¥1.5B (est.)	gov, SOEs, gaming cos.

Strategic Positioning​

Vendor	Tech route	Core strength	Main challenge
Huawei Ascend	AI-training-specific (Da Vinci)	co-optimized HW/SW, carrier channels	sanctions, process limits
Cambricon	AI-training-specific (MLUarch)	high efficiency, competitive price	immature ecosystem
Moore Threads	Full-function GPU (MUSA)	graphics + AI + general compute, Day-0 support	compute below dedicated AI chips

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II. Flagship Product Comparison​

1. Huawei Ascend 950DT (2026 flagship)​

Item	Spec
BF16 compute	1,000 TFLOPS
Memory	144GB HiZQ 2.0 (in-house HBM)
Memory bandwidth	4 TB/s
TDP	400W
Process	N+2 (improved 7nm)
Released	2026-04
Mass production	2026-Q2
Unit price	~¥80,000 (est.)

Strengths:

• ✅ High large-model inference throughput: 144GB memory friendly to DeepSeek R1 (671B MoE)
• ✅ Most mature ecosystem: CANN ~85% operator coverage, supports PyTorch, TensorFlow
• ✅ Strong carrier channel: China Mobile, China Telecom large purchases

Weaknesses:

• ❌ Process limited: N+2 below TSMC 4nm
• ❌ Mediocre efficiency: 400W TDP, 2.5 TFLOPS/W

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2. Cambricon MLU690 (2026 flagship)​

Item	Spec
BF16 compute	600 TFLOPS
Memory	64GB HBM3
Memory bandwidth	2 TB/s
TDP	280W
Process	TSMC 7nm
Released	2025-Q4
Mass production	2026-Q1
Unit price	~¥140,000 (est.)

Strengths:

• ✅ Best efficiency: 280W TDP, 2.14 TFLOPS/W (1.5x H100)
• ✅ Competitive price: ~$20,000, 33% cheaper than H100
• ✅ Top-tier customer orders: ByteDance, Alibaba, Baidu

Weaknesses:

• ❌ Small memory: 64GB limits large-model training scale
• ❌ Immature ecosystem: NeuWare ~75–85% coverage; complex LLMs need manual tuning

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3. Moore Threads MTT S5000 (2025 flagship)​

Item	Spec
FP16 compute	~1,000 TFLOPS (est.)
Memory	80GB GDDR6X
Memory bandwidth	1.6 TB/s
TDP	~350W
Process	TSMC 4nm (est.)
Released	2025-02
Mass production	2025-Q2
Unit price	~¥50,000 (est.)

Strengths:

• ✅ Full-function GPU: graphics + AI + general compute, broader scenarios
• ✅ Strong Day-0 support: June 2026 Day-0 support for Qwen3.5, GLM-5.2, MiniMax M3
• ✅ Lowest price: ~¥50,000, high cost-performance

Weaknesses:

• ❌ Compute below dedicated AI chips: FP16 ~50% of H100
• ❌ Low memory bandwidth: 1.6 TB/s (48% of H100), limits large-model training

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III. Compute Comparison (BF16/FP16)​

Chip	BF16 compute	Memory	Bandwidth	TDP	Efficiency
Huawei Ascend 950DT	1,000 TFLOPS	144GB	4 TB/s	400W	2.5 TFLOPS/W
Cambricon MLU690	600 TFLOPS	64GB	2 TB/s	280W	2.14 TFLOPS/W
Moore Threads MTT S5000	~1,000 TFLOPS	80GB	1.6 TB/s	~350W	~2.86 TFLOPS/W
NVIDIA H100	989 TFLOPS	80GB	3.35 TB/s	700W	1.41 TFLOPS/W
NVIDIA H200	989 TFLOPS	141GB	4.8 TB/s	700W	1.41 TFLOPS/W

Key insights:

1. Ascend 950DT has the highest compute (1,000 TFLOPS) but mediocre efficiency
2. Cambricon MLU690 has the best efficiency (2.14 TFLOPS/W), TDP only 280W
3. Moore Threads MTT S5000 wins on full-function versatility but low bandwidth

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IV. Software Ecosystem​

Vendor	Stack	Framework support	Coverage	Maturity
Huawei Ascend	CANN	PyTorch, TensorFlow, MindSpore	~85%	⭐⭐⭐⭐ (4/5)
Cambricon	NeuWare	PyTorch-Cambricon, TensorFlow-Cambricon	~75–85%	⭐⭐⭐ (3/5)
Moore Threads	MUSIFY	PyTorch, TensorFlow, ONNX	~70%	⭐⭐⭐ (3/5)
NVIDIA	CUDA	all	~99%	⭐⭐⭐⭐⭐ (5/5)

Ecosystem Maturity Assessment​

Huawei Ascend CANN:

• ✅ Strength: highest operator coverage, supports MindSpore (in-house framework)
• ❌ Weakness: steep learning curve, incomplete docs

Cambricon NeuWare:

• ✅ Strength: PyTorch/TensorFlow compatible, low migration cost
• ❌ Weakness: complex LLMs need manual tuning

Moore Threads MUSIFY:

• ✅ Strength: strong Day-0 support, ONNX support
• ❌ Weakness: lowest operator coverage, dual graphics+AI engine complexity

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V. Commercial Progress​

Vendor	2026 commercial progress	Main customers	Shipments
Huawei Ascend	Ascend 950 mass production; China Mobile large purchase	China Mobile, China Telecom, gov	~100K/yr (est.)
Cambricon	MLU690 mass production; ByteDance, Alibaba orders	ByteDance, Alibaba, Baidu	~50K/yr (est.)
Moore Threads	MTT S5000 mass production; Day-0 Qwen3.5	gov, SOEs, gaming cos.	~30K/yr (est.)

Latest as of June 2026​

Huawei Ascend:

• ✅ Ascend 950DT fully ramping
• ✅ ¥1B procurement agreement with China Mobile

Cambricon:

• ✅ MLU690 in volume shipment
• ✅ ByteDance order ~20K units

Moore Threads:

• ✅ Day-0 support for Qwen3.5, GLM-5.2, MiniMax M3
• ✅ MTT S5000 2nd-gen released

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VI. Selection Advice​

Scenario 1: Trillion-parameter training (GPT-4 class)​

Recommended: Huawei Ascend 950DT

• ✅ 144GB large memory supports super-large models
• ✅ Most mature ecosystem (~85% coverage)
• ✅ Strong carrier channel, Chinese government backing

Alternative: Cambricon MLU690 (high efficiency, but small memory)

Scenario 2: Tens-to-hundreds-of-billions parameter training​

Recommended: Cambricon MLU690

• ✅ Best efficiency (2.14 TFLOPS/W), low TCO
• ✅ Competitive price (~$20,000)
• ✅ Validated by top customers (ByteDance, Alibaba)

Alternative: Huawei Ascend 920 (more compute, mediocre efficiency)

Scenario 3: Cloud AI inference​

Recommended: Huawei Ascend 950PR (inference-specific)

• ✅ Well-optimized inference throughput
• ✅ 128GB memory friendly to MoE models
• ✅ Mature stack, low deployment cost

Alternative: Moore Threads MTT S5000 (full-function GPU, inference + graphics)

Scenario 4: Edge AI / on-device inference​

Recommended: Moore Threads MTT S5000

• ✅ Full-function GPU, graphics + AI
• ✅ Lowest price (~¥50,000)
• ✅ Strong Day-0 support

Alternative: Huawei Ascend 310 (low power, 8W TDP)

Scenario 5: Domestic substitution (gov, SOEs)​

Recommended: Huawei Ascend 950DT

• ✅ Chinese government first choice, carrier bulk buys
• ✅ Co-optimized HW/SW, stable performance
• ✅ Supported by national semiconductor fund

Alternative: Cambricon MLU690 (high efficiency, competitive price)

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VII. Future Roadmap​

Vendor	2026 H2	2027	2028
Huawei Ascend	950DT ramp	960 (FP8 ~2 PFLOPS)	970 (N+3 process)
Cambricon	MLU690 ramp	MLU790 (5nm, BF16 ~1,000 TFLOPS)	MLU890 (3nm)
Moore Threads	MTT S5000 2nd-gen	MTT S6000 (HBM3, FP16 ~1,500 TFLOPS)	MTT S7000

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VIII. Summary: Who Is the "China H100"?​

Dimension	Ascend 950DT	MLU690	MTT S5000
Compute	⭐⭐⭐⭐⭐ (5/5)	⭐⭐⭐ (3/5)	⭐⭐⭐ (3/5)
Memory	⭐⭐⭐⭐⭐ (5/5)	⭐⭐ (2/5)	⭐⭐⭐ (3/5)
Efficiency	⭐⭐⭐ (3/5)	⭐⭐⭐⭐⭐ (5/5)	⭐⭐⭐⭐ (4/5)
Ecosystem	⭐⭐⭐⭐ (4/5)	⭐⭐⭐ (3/5)	⭐⭐⭐ (3/5)
Price	⭐⭐⭐ (3/5)	⭐⭐⭐⭐ (4/5)	⭐⭐⭐⭐⭐ (5/5)
Overall	⭐⭐⭐⭐ (4/5)	⭐⭐⭐ (3/5)	⭐⭐⭐ (3/5)

Final conclusion:

• Huawei Ascend 950DT is the domestic AI training chip closest to H100, strongest overall
• Cambricon MLU690 is the most efficient domestic AI chip, lowest TCO
• Moore Threads MTT S5000 is the cheapest full-function GPU, suited to edge AI and graphics+AI

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References​

• Huawei Ascend 950 series — MirrorFrog detailed specs
• Cambricon MLU690 — MirrorFrog detailed specs
• Moore Threads MTT S5000 — MirrorFrog detailed specs
• Full AI chip comparison table — 100+ chip specs
• 2026 H2 AI chip roadmap major update — latest roadmap

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Disclaimer: Data based on public sources; actual specs per vendor official. MirrorFrog continuously updates domestic AI chip data — corrections welcome.

Changelog: 2026-06-23 initial release

June 2026 update — the AI compute card market is undergoing its most dramatic reshuffling in years. This article walks through the latest roadmap developments.

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Key Takeaways​

• Qualcomm AI 200/250 officially enters the datacenter AI inference market, targeting NVIDIA H200
• AMD MI400 series unveils three models: MI430X (HPC), MI440X (enterprise), MI455X (flagship)
• Huawei publishes a three-generation roadmap: 950 (2026) → 960 (2027-Q4) → 970 (2028-Q4)
• Intel Jaguar Shores timeline uncertain, possibly delayed to 2027 or later
• NVIDIA Rubin R200 is in full mass production; the Vera CPU + Rubin GPU combination is now shipping

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1. Qualcomm: Mobile Giant Moves Into Datacenter AI​

AI 100 → AI 200 → AI 250​

Qualcomm officially launched the AI 200 datacenter inference chip in October 2025, marking the mobile giant's formal entry into the datacenter AI market.

Model	Launch	Availability	Key Features
AI 100	2025-10	2026 H2	Rack-scale AI inference, 768GB LPDDR per card
AI 250	2025-10	2027 H1	Near-memory computing architecture, 10x effective memory bandwidth

Why Qualcomm Can Succeed​

1. Low TCO: LPDDR memory is far cheaper than HBM
2. Energy efficiency: Mobile chip design heritage, excellent power control
3. Inference-focused: Not chasing training performance, focused on inference scenarios
4. Rack form factor: Direct liquid cooling, 160kW rack-level power, Ethernet interconnect

Market Impact​

• Takes on NVIDIA H200: AI 200 inference performance approaches H200 but with 30-40% lower TCO
• Pressures NVIDIA: May push NVIDIA to launch inference-specific chips (e.g., Rubin CPX)
• Diversifies choice: Breaks NVIDIA's monopoly in the inference market

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2. AMD MI400 Series: Three Models, Precise Positioning​

At CES 2026 (January 2026), AMD officially unveiled the three models of the MI400 series, precisely covering different markets:

MI430X (HPC + Sovereign AI)​

Feature	Spec
Positioning	HPC + sovereign AI
FP32/FP64	Supported (key differentiator)
Use cases	Scientific computing, climate simulation, national AI infrastructure
Competitor	NVIDIA does not make FP64 AI cards

MI440X (Enterprise Servers)​

Feature	Spec
Positioning	Enterprise 8-GPU servers
Compatibility	Works with existing datacenter infrastructure
Use cases	Enterprise AI, private cloud, edge inference
Advantage	Cheaper and easier to deploy than MI455X

MI455X (Flagship AI Training)​

Feature	Spec
Positioning	Flagship AI training + inference
Optimized precision	FP4/FP8/BF16
Helios rack	Core component
Competitor	NVIDIA Rubin R200

Helios Rack-Scale Solution​

AMD also launched the Helios rack-scale AI solution at CES 2026:

• 18 Zen 6 CPUs (2nm process)
• 72 MI455X GPUs
• Direct liquid cooling
• Shipment expected in 2026 H2

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3. Huawei Three-Generation Roadmap: 950 → 960 → 970​

Huawei unveiled its three-generation chip roadmap at HC 2025 (September 2025) with a very clear timeline:

Ascend 950 Series (2026)​

Model	Launch	Key Features
950PR	2026-Q1	PR (inference-optimized), already in mass production
950DT	2026-Q4	DT (Decode + training), expected to scale up

Technical highlights:

• Added FP8/MXFP8/MXFP4 support
• Interconnect bandwidth 2TB/s (2.5x over 910C)

Ascend 960 (2027-Q4)​

• Doubled compute: All specs double versus the 950 series
• FP8: ~2 PFLOPS expected
• Process: N+3 (equivalent to 5nm)
• Positioning: Targets NVIDIA B200

Ascend 970 (2028-Q4)​

• Third-generation flagship: Only timeline announced, specs TBD
• Significance: Huawei's first complete generation-spanning roadmap
• Signal: China's domestic AI chips have entered a "roadmap-driven" phase

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4. Intel Jaguar Shores: Timeline Uncertain​

Original Plan​

• Launch: 2026
• Architecture: Xe-HPC + Gaudi fusion
• Process: 18A (Intel's most advanced)
• Memory: Possibly HBM4E (instead of originally planned HBM4)

Latest Developments​

• Possible delay: Some sources suggest a slip to 2027
• Competitors: AMD MI400 already unveiled, NVIDIA Rubin in mass production
• Market pressure: Intel is losing ground in the AI chip market; Jaguar Shores is its last chance

Impact on Roadmap​

If Jaguar Shores slips to 2027, Intel will essentially be out of the AI chip market.

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5. NVIDIA Rubin Platform: Full Mass Production​

Rubin R200 (2026-Q2 full mass production)​

Feature	Spec
HBM	288GB HBM4
Compute	50 PFLOPS FP4
NVLink	NVLink 6 (1800 GB/s)
Process	TSMC 4NP

Rubin NVL72 Cabinet (2026 H2 shipment)​

• 72 Rubin GPUs
• 36 Vera CPUs
• 1.8 EFLOPS FP4
• Direct liquid cooling

Vera CPU (Debut)​

• Architecture: Custom CPU replacing Grace
• Positioning: Deep co-design with Rubin GPU
• Significance: NVIDIA's transformation from a GPU company into a computing platform company

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6. Google TPU v8: Training/Inference Officially Split​

TPU 8t (training) + TPU 8i (inference)​

At Cloud Next 2026, Google announced TPU v8 would officially split into training and inference versions:

Feature	TPU 8t (training)	TPU 8i (inference)
Optimization	High compute, high bandwidth	Low latency, low cost
Interconnect	Optical interconnect	Ethernet
Launch	2027	2027

Significance​

• Industry trend: Specialization of training/inference chips
• Followers: Qualcomm AI 200 is also inference-only
• NVIDIA pressure: Does it need an inference-specific chip?

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7. Cerebras WSE-4: Wafer-Scale Engine Evolves​

Core Specs​

Feature	Spec
Transistors	1.4 trillion
Compute	125 PFLOPS FP8
Launch	2026 H2
Process	TSMC 5nm

Competitive Advantages​

• Massive model training: A single WSE-4 can train 10T+ parameter models
• Low-latency inference: Entire model on one chip, no communication overhead
• Mature software stack: Cerebras stack already supports PyTorch, TensorFlow

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8. Market Landscape Analysis​

Training Market​

Rank	Vendor	Product	Market Share (est.)
1	NVIDIA	Rubin R200	70%
2	AMD	MI455X	15%
3	Google	TPU v8t	10%
4	Huawei	Ascend 960	5% (mostly China)

Inference Market (New Battlefield)​

Rank	Vendor	Product	Advantage
1	NVIDIA	H200 / Rubin CPX	Mature ecosystem
2	Qualcomm	AI 200	Low TCO
3	AMD	MI440X	Good compatibility
4	Intel	Gaudi 4	Low price

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9. Key Trends​

Trend 1: Rise of Inference-Specific Chips​

• Qualcomm AI 200: Mobile giant enters the market
• NVIDIA Rubin CPX: NVIDIA's first inference-specific chip
• Google TPU 8i: Training/inference officially split

Trend 2: Rack-Scale Solutions Become Standard​

• NVIDIA NVL72: 72 GPU + 36 CPU
• AMD Helios: 18 CPU + 72 GPU
• Qualcomm rack: 160kW liquid-cooled rack

Trend 3: China's Domestic Chips Enter "Roadmap-Driven" Phase​

• Huawei three-generation roadmap: 950 → 960 → 970
• Clear timeline: 2026-Q1 → 2027-Q4 → 2028-Q4
• Significance: From "catch-up" to "planning"

Trend 4: HBM Capacity Becomes the Bottleneck​

• SK hynix: HBM4 capacity already booked by NVIDIA
• Samsung: HBM4E samples delivered to AMD
• Impact: MI400 and Rubin R200 shipments constrained by HBM capacity

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10. Procurement Recommendations​

If Procuring in 2026 H2​

1. Training scenarios:

   • First choice: NVIDIA Rubin R200 (best performance)
   • Alternative: AMD MI455X (better price/performance)
   • Domestic: Huawei Ascend 950DT (China-based customers)

2. Inference scenarios:

   • First choice: NVIDIA H200 (mature ecosystem)
   • Best value: Qualcomm AI 200 (if available)
   • Cost-sensitive: AMD MI440X

3. HPC scenarios:

   • Only choice: AMD MI430X (FP64 support)

If Procuring in 2027​

• Wait for Rubin Ultra: Performance possibly 2x R200
• Watch MI500: AMD's next-generation product
• Evaluate TPU v8: If already on Google Cloud

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Conclusion​

2026 H2 will be the most fiercely contested half-year in AI chip market history:

• NVIDIA continues to lead, but its advantage is narrowing
• AMD precisely positions three models; market share will keep rising
• Qualcomm enters the inference market; its low-TCO strategy may disrupt the market
• Huawei has a clear three-generation roadmap; domestic substitution accelerates
• Intel's Jaguar Shores is make-or-break

For procurement decision-makers, this is the hardest time to decide — every option has clear pros and cons.

For engineers, this is the best of times — chip performance doubles yearly, architectural innovation is endless.

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References​

• AI Compute Card Future Roadmap - MirrorFrog real-time updates
• NVIDIA Rubin R200 deep dive (see related articles on this site)
• AMD MI400 series CES 2026 launch (see related articles on this site)
• Qualcomm AI 100 launch analysis (coming soon)

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Last updated: 2026-06-20
Author: Charles Qing
Tags: #roadmap #market-analysis #procurement

On June 5, 2026, Shenzhen announced a major piece of news: Shenzhen Hetao College, together with HIT (Shenzhen) and Huawei, used 1,000 Huawei Ascend 910C chips to successfully complete full-parameter post-training of the 1.6-trillion-parameter DeepSeek-V4-Pro large model.

This was no tentative attempt, but a milestone technological breakthrough. It proved with irrefutable engineering results that: domestic AI chips are fully capable of supporting world-class, super-large-parameter model training.

Why this matters​

The two thresholds of AI chips: "inference" and "training"​

• Inference: using an existing model to chat, write copy. Domestic chips could already do this
• Training: adjusting model parameters to learn new capabilities. Full-parameter training adjusts all 1.6 trillion parameters at once — maximum difficulty

Previously, full-parameter training of trillion-scale models was monopolized by NVIDIA H100/H200. Domestic chips could only do inference, not large-scale training.

The significance of this breakthrough: domestic compute leapt from "usable" to "useful", from "inference" to "training".

Technical details​

Training configuration​

Item	Parameter
Chips	Huawei Ascend 910C × 1,000
Model	DeepSeek-V4-Pro
Parameters	1.6 trillion (1600B)
Training type	Full-parameter post-training
Framework	MindSpore + torch_npu
Completed	Announced June 5, 2026

Performance metrics​

Metric	Value	Assessment
Compute utilization	>30%	Industrial grade (top overseas chips ~40%)
Key training operator efficiency	+14%	vs previous-gen 910B
Communication bandwidth utilization	>60% (est.)	MoE All-to-All communication
Stability	1,000 cards trained continuously with no failures	Cluster stability met standard

💡 About 30% compute utilization: many feel 30% is low, but in large-model training this is already a very respectable industrial-grade level. Even with the most advanced overseas chips, many teams' actual utilization is around 40%.

Ascend 910C detailed specs​

Ascend 910C is Huawei's AI training/inference chip announced at the Huawei Analyst Conference (April 24, 2024), with a theoretical peak of 800 TFLOPS (BF16), in the same class as NVIDIA H100.

Parameter	Ascend 910C	Ascend 910B	NVIDIA H100
Architecture	Ascend 910C	Ascend 910B	Hopper
Process	TSMC 7nm (est.)	TSMC 7nm	TSMC 4NP
BF16 compute	800 TFLOPS	256 TFLOPS	989 TFLOPS (sparse)
Memory	64GB HBM (est.)	64GB HBM2e (B1/B2)	80GB HBM3
Memory bandwidth	~2TB/s (est.)	600 GB/s (B1/B2)	3.35 TB/s
TDP	~400W (est.)	300-400W	700W
Mass production	April 2026 (full production)	Nov 2022	Mar 2022

Key upgrades:

• ✅ 3× compute: from 910B's 256 TFLOPS to 800 TFLOPS
• ✅ Mature software ecosystem: torch_npu adapts PyTorch, MindSpore framework mature
• ✅ Cluster stability: 1,000 cards trained continuously with no failures (the biggest breakthrough)

Technical challenges and solutions​

Challenge 1: Memory demand of trillion-scale models​

A 1.6-trillion-parameter model needs, just for model parameters:

• FP16: 1.6T × 2 bytes = 3.2 TB
• Plus gradients and optimizer states: at least 10 TB of memory

Huawei's solution:

• Model Parallel: distribute the model across 1,000 910C chips
• ZeRO optimizer: optimize memory footprint
• Gradient accumulation: update parameters in stages

Challenge 2: Communication efficiency of thousand-card clusters​

Training with 1,000 chips, inter-chip communication becomes the bottleneck. MoE models need All-to-All communication (each expert may need to communicate with all others).

Huawei's solution:

• HCCS (Huawei Collective Communication Scheduler): in-house high-speed interconnect protocol
• Layered communication: intra-node NVLink + inter-node HCCS
• Communication-compute overlap: data transfer concurrent with computation

Challenge 3: Training stability​

Trillion-scale model training takes weeks or months; any single card failure can interrupt the entire training.

Huawei's solution:

• Fault detection and auto-recovery: real-time monitoring of card status, auto-restart and recovery on failure
• Checkpoint optimization: high-frequency training-state saves (every N steps)
• Ascend cluster management software: designed specifically for enterprise training

Competitive comparison​

Vendor	Chip	1.6T-param training	Ecosystem maturity	Availability
Huawei	Ascend 910C	✅ Completed	⭐⭐⭐ (improving)	China-localized
NVIDIA	H100/H200	✅ Industry standard	⭐⭐⭐⭐⭐	Global (export-controlled)
AMD	MI300X	✅ Feasible	⭐⭐⭐⭐	Global
Google	TPU v5p/8t	✅ JAX-native	⭐⭐⭐⭐	Google Cloud

Conclusion: Ascend 910C has caught up to H100 in hardware performance, still lags in software ecosystem, but this training success proves engineering feasibility.

Industry impact​

1. The "Zunyi Conference" of domestic compute​

This breakthrough is called the "Zunyi Conference" of domestic compute — from passive defense to strategic counteroffensive.

Specific impact:

• ✅ Breaks the bias that "domestic chips can only do inference"
• ✅ Proves domestic chips can train frontier models
• ✅ Provides compute foundation for domestic large models (e.g., DeepSeek-V4, ERNIE 5.0)

2. Impact on NVIDIA​

Huawei Ascend 910C completing trillion-scale training means China's AI industry is less dependent on NVIDIA.

Scenario	Before	Now
Inference	Domestic chips usable	Domestic chips useful
Training	Must use H100/H200	Can use 910C
Large-scale training	Must use H100 clusters	Can use 910C clusters

3. Boost to the domestic chip industry​

This breakthrough will drive the entire domestic AI chip supply chain:

• Chip design: Cambricon, MetaX, Moore Threads accelerate iteration
• Wafer manufacturing: SMIC, Hua Hong get more orders
• Packaging/test: JCET, TFME benefit

Huawei Ascend roadmap (2025-2028)​

Time	Chip	Positioning
Q1 2025	Ascend 910C	Flagship training/inference (mass-produced)
Q1 2026	Ascend 950PR	Inference-optimized (~500 TFLOPS BF16)
Q4 2026	Ascend 950DT	Data-center training
Q4 2027	Ascend 960	Next-gen flagship
Q4 2028	Ascend 970	Next-next-gen

Training lessons shared​

The Shenzhen Hetao College team accumulated valuable experience:

✅ Successes​

1. Progressive training: start from small models (7B), gradually scale to 1.6T
2. Mixed-precision training: BF16 main + FP32 gradient accumulation
3. Communication optimization: All-to-All overlap with computation
4. Fault recovery: save checkpoint every 1,000 steps

⚠️ Challenges encountered​

1. Memory fragmentation: severe fragmentation over long training, needs periodic cleanup
2. Communication bottleneck: MoE All-to-All takes 30%+ of training time
3. Software bugs: torch_npu occasional memory leak, needs training process restart

Related chips​

• Huawei Ascend 910C - the chip used in this training
• Huawei Ascend 910B - previous-gen chip
• Huawei Ascend 950PR - next-gen inference chip
• NVIDIA H100 - benchmark product
• NVIDIA H200 - benchmark product (HBM3e upgrade)

References​

• Sina Finance: Huawei Ascend 910C completes DS-V4-Pro training
• Tencent News: Milestone! Ascend 910C completes 1.6-trillion-param model training
• 21IC: Huawei chip completes full-parameter post-training of 1.6T AI model

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This article is compiled from public reports. Salute to the teams at Shenzhen Hetao College, HIT (Shenzhen), and Huawei — you proved the feasibility of China's AI compute with engineering results.