14 posts tagged with "Huawei"

This article is based on market analysis published by Bloomberg Intelligence and Bernstein in September 2026 and public reporting; market share and revenue figures are analyst estimates, not official disclosures.

On September 28, two Wall Street reports simultaneously painted a dramatic picture: the balance of market share in China's AI compute market completed an almost total flip within 12 months.

1. The Share Flip: 40% to 8%, Ascend to 50%​

Bernstein's latest forecast:

• NVIDIA's share of the China AI chip market will fall from about 40% to about 8% by the end of this year
• Huawei Ascend rises to nearly 50%
• The immediate trigger: China's September ban on new H20 orders from NVIDIA, which shut the last channel for NVIDIA's return to the Chinese market
• ByteDance, Alibaba, and Tencent have all placed large Ascend orders

On the timeline, this was not a sudden shock but the cumulative result of three years of tightening export controls: NVIDIA's share of the China AI chip market once peaked at 95%; as high-end chips were cut off, Chinese hyperscale cloud providers pivoted wholesale to Huawei and domestic alternatives. Even when Washington allowed H200 sales to China in January 2026, the gears of that shift had already meshed — there was no going back.

2. Ascend 950PR: The "Chinese H200" in Analysts' Eyes​

What underpins this share data is product strength itself:

• The Ascend 950PR entered mass production in March this year, with FP4 compute of up to 2 PFLOPS and 128GB of domestic HBM
• Analysts rate it as roughly on par with the NVIDIA H200
• Huawei's AI chip revenue is expected to reach $12 billion this year, up 60% from $7.5 billion in 2025

For the full specifications of the 950 series, see our earlier in-depth articles: Ascend 950PR/950DT Dual-Configuration Analysis and Ascend 960 Official Launch — the 960 was ready three quarters ahead of schedule, confirming a one-generation-per-year cadence.

3. The Model Side: Chinese Open Models Take the OpenRouter Token Pie​

While chip shares flipped, the model usage data is equally striking (OpenRouter platform statistics):

Metric	Data
DeepSeek token share (June)	16.3%, surpassing Google, Anthropic, and OpenAI individually to rank first
Combined token share of Chinese open-weight models (May)	About 61% (DeepSeek, Qwen, MiniMax, Tencent Hunyuan, etc.)
Weekly token consumption of Chinese models	About 18 trillion, versus about 5.5 trillion for US models — a gap of more than 3x, with the overtake completed within a year
China-US frontier model performance gap (June)	Narrowed to 6%, a historic low (9% in May)

Compute and models form a positive feedback loop: cards that cannot be bought force domestic compute to scale up; scaled-up domestic compute produces cheap tokens; and cheap tokens let Chinese open-source models swallow the bulk of global inference traffic.

4. But the Stock Market Isn't Buying It​

Bloomberg Intelligence pointed out a contradiction in the same period: the valuation discount of the China Tech 8 relative to the US Magnificent Seven has widened to more than 50%, the widest of the year, and BI believes only a "true AI breakthrough" can close it. Year-to-date stock performance: Alibaba about -7%, Tencent about -23%, while US AI infrastructure leaders broadly gained more than 15%.

There are two readings of this divergence: either the market is underestimating China's AI fundamentals, or earnings execution (Alibaba's EPS missed expectations by 17.3% last quarter, Baidu's by 36%) has dragged down the delivery of the AI narrative. For industry observers, the notable point is: the compute-side data (share, revenue, shipments) has moved ahead, while application-side monetization is still on the way.

5. Three Takeaways for Compute Buyers​

1. For deployments in China, the Ascend ecosystem is already the default option. The cost of migrating from CUDA to CANN is one-time, while supply uncertainty is persistent; after the September ban, there is no compliant path to procuring new NVIDIA cards in the Chinese market.
2. Domestic compute "matching the H200" is a watershed. The implicit assumption of domestic substitution used to be "discounted performance, discounted price"; when single-card performance catches up to the H200 generation, procurement decisions return to pure TCO and supply-security calculations — we recommend using the TCO Calculator to put electricity, depreciation, and utilization into the same table.
3. The token cost curve determines the application landscape. Chinese models' 61% share of OpenRouter tokens shows that the chain of compute self-sufficiency leading to token price drops leading to application prosperity has completed its first leg; the next question is whether inference costs can keep falling.

Summary​

From 40% to 8% is not a slogan but a market reshuffle driven jointly by the ban, product strength, and the model ecosystem. For the Chinese market, the mass-production cadence of Ascend 950/960 and the maturity of the CANN ecosystem will determine whether this share can be held; for the global market, the combination of China's compute "internal circulation + open-source models going overseas" is rewriting the geographic distribution of inference traffic.

(Market share and revenue forecasts come from Bernstein / Bloomberg Intelligence analyst reports; actual figures are subject to each company's financial reports.)

On September 22, 2026, multiple media outlets reported that DeepSeek's CEO explicitly stated the company is betting heavily on Huawei chips, expects to receive a new batch of Huawei chips for large-model training, and stressed that "this choice must succeed." Following earlier reports that "DeepSeek planned to procure 160,000 Ascend 950DT units for inference," this is the most significant alignment signal yet in the domestic compute ecosystem — an upgrade from inference procurement to a training bet.

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1. The Signal Chain: Four Steps to a "Training Bet"​

Piecing together the public information from the past six months, the DeepSeek–Ascend collaboration shows a clear escalation path:

Time	Signal	Nature
Mid-2026	DeepSeek V4 completes ecosystem migration from CUDA to CANN	Software adaptation
August 2026	Report: DeepSeek plans to procure 160,000 Ascend 950DT units for inference deployment	Inference procurement intent
2026-09-17	HC2026: 960DT ready three quarters ahead of schedule, 950DT ramping in Q4	Supply delivery
2026-09-22	DeepSeek CEO: betting on Huawei chips for LLM training, "must succeed"	Training bet

The key change is the workload tier: inference deployment means "cutting costs with off-the-shelf compute," while a training bet means "staking the existence of next-generation models on domestic chips" — training clusters demand an order of magnitude more in stability, interconnect efficiency, and software-stack maturity.

2. Huawei's Ability to Deliver​

DeepSeek's willingness to commit rests on a series of verifiable progress points on Huawei's supply side (all official figures):

• One generation per year, delivered: the 950PR is in mass production, the 950DT ramps in 2026 Q4, and the 960DT moved three quarters earlier than its original 2027 Q4 plan to ready in 2027 Q1 / launch in Q2 — the roadmap's credibility validated twice in a row;
• Deployment scale: Ascend supernodes have been commercially deployed at scale in over 1,000 sets, covering internet, finance, healthcare, and manufacturing;
• Ecosystem maturity: CANN has entered routine open-source operation, with external developers exceeding 61% for the first time and 5,200 monthly active developers; there are over 40 Ascend-native training models, making it the only domestic technology route supporting pretraining;
• Training evidence chain: China Telecom's Xing 4.0-29B-A4B agentic MoE model, open-sourced in September, was announced as trained end-to-end on Ascend (company claim) — "Ascend can train large models" is no longer just Huawei's self-attestation.

See the Ascend 950DT and Ascend 960 spec pages for details; for supernode analysis, see Ascend 960 Official Launch.

3. Why DeepSeek?​

DeepSeek's choice has strong structural drivers:

1. Supply certainty: under export-control constraints, NVIDIA's flagship supply to China keeps tightening; domestic compute is the only plannable large-scale training supply;
2. Cost structure: DeepSeek has always been known for extreme engineering efficiency (the V3 training cost set the industry benchmark), and domestic compute plus supernode system efficiency fits its approach;
3. Betting on ecosystem dividends: CANN open-sourcing plus deep binding with leading model vendors means model vendors can participate in shaping the toolchain's direction — something impossible within CUDA's closed system;
4. Self-fulfilling demonstration effect: a leading lab's public commitment pulls back on Huawei's production scheduling and upstream HBM and system investment, making "must succeed" a rational commitment rather than a slogan.

4. Risks and Open Questions​

Viewed coolly, this route still has three items that need time to verify:

• Actual training scale: the quantity, model type (950DT or 960DT), and delivery schedule of the new batch of chips are all undisclosed;
• MFU methodology: the MFU / latency gains Huawei cites all come from Markov-lab simulations, with no independent third-party measurements yet; the real effective compute of a training cluster depends on long-term data from large-scale production environments;
• Per-card generation gap: the 960DT's 4 PFLOPS (FP4) versus Rubin R200's 50 PFLOPS (FP4) — the per-card gap objectively exists, and training efficiency depends on whether supernode scale and software optimization can compensate; that is precisely the decisive battleground of "system-level competition."

5. Summary​

• DeepSeek confirms betting on Huawei chips for training large models — the first training-grade commitment from a leading lab in domestic compute;
• Signal chain: CUDA→CANN migration → 160,000-unit 950DT inference procurement rumor → 960 ready ahead of schedule → training bet;
• Supporting factors: one-generation-per-year delivery, 1,000+ supernode sets, and 61% external developers in the CANN open-source ecosystem;
• What to watch: actual arrival of the new chips and training-cluster scale, third-party MFU data, and training-compute disclosure in DeepSeek's next release.

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Further Reading​

• Ascend 960 spec page / Ascend 950DT spec page (this site)
• Ascend 960 Official Launch: FP4 Compute Doubled, World's First NPO Supernode
• Domestic Top Three in H2 2026: Localization Rate Breaks 40%, Heading Toward 60%
• Alibaba Zhenwu V900 Unveiled at Apsara Conference

References​

• Toutiao Tech Morning Report: DeepSeek confirms betting on Huawei chips for large-model training (2026-09-22)
• HUAWEI CONNECT 2026 official announcements (2026-09-17)
• Earlier report: DeepSeek plans to procure 160,000 Ascend 950DT units (2026-08)

This article is compiled from public reports and vendors' official statements. Details such as chip quantities and training-cluster scale are subject to subsequent disclosures from DeepSeek and Huawei.

2026 年 9 月 17 日，华为全联接大会（HC2026），华为常务董事、ICT 基础设施业务总裁汪涛正式发布昇腾 960。与 8 月数字中国峰会上的"路线图预告"不同，这次是完整的规格官宣——而且提前三个季度就绪。本文基于华为官网新闻稿及多方报道整理，逐项拆解 960 的规格、超节点与路线图含义。

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1. 昇腾 960：双版本，训练先行​

昇腾 960 分为两个版本，节奏错开一个季度：

指标	昇腾 960DT（训练版）	昇腾 960PR（推理版）
FP8 算力	2 PFLOPS（较 950 翻倍）	待披露
FP4 算力	4 PFLOPS	待披露
显存	288GB（自研 HBM）	待披露
显存带宽	9.6 TB/s	待披露
配套超节点	Atlas 860（风冷）	Atlas 960（液冷）
就绪 / 上市	2027 Q1 / 2027 Q2	2027 Q3

三个读数：

• 提前三个季度就绪：960DT 原计划 2027 年 Q4，现在 2027 Q1 就绪、Q2 上市——与 950DT"提前上线华为云"一脉相承，路线图可信度在持续兑现；
• 精度口径与英伟达对齐：FP8 / FP4 主口径（辅以自研 HiF8 / HiFP8），FP4 已是 2026 新卡的通用口径；
• 288GB 自研 HBM + 9.6TB/s：显存容量与带宽同步翻倍，对训练长上下文大模型是实打实的容量红利。

单卡规格详见昇腾 960 规格页；上一代昇腾 950DT 规格页。

2. 昇腾 960 超节点：全球首个 NPO 超节点​

这是本场发布真正的"重器"——昇腾 960 超节点是全球第一个采用 NPO（近封装光学）的超节点：

指标	昇腾 960 超节点
单节点规模	4096 卡
系统算力	8 EFLOPS FP8 / 16 EFLOPS FP4
HBM 总容量	1 PB
互联 RTT	低至 2μs
可用度	99.8%

NPO 意味着什么：传统光模块挂在交换机面板上，信号要先出封装再转电—光；NPO 把光引擎挪到交换芯片封装近旁，大幅缩短 SerDes 距离、降低功耗与时延。华为的具体数字：

• 5500 个自研 Hi-ONE 光引擎（业界首个量产 NPO，单引擎 7.2T）；
• 替代 4.8 万颗 800G 光模块；
• 降低功耗 550kW 以上，同时支撑 2μs 级互联时延。

对比 8 月数字中国峰会的口径（Atlas 960 单超节点 15488 卡），官方最新口径为单超节点 4096 卡（1 个超集群可由多超节点组成）——以华为官网最新新闻稿为准。

⚠️ 华为还给出了"MFU 提升 2.75 倍""推理时延降低 70%"等收益数据，均出自华为马尔科夫实验室仿真，尚无独立第三方实测，阅读时注意口径。

3. 一年一代：970（2028）→ 980（2029）​

华为首次把"一年一代"从愿景变成官宣承诺：

年份	产品	状态
2026	昇腾 950 系列	950PR 已量产，950DT Q4 放量
2027	昇腾 960	本次官宣，提前就绪
2028	昇腾 970	HC2026 确认
2029	昇腾 980	HC2026 确认

支撑这一节奏的是华为提出的"韬定律"：算力规格每代翻倍，访存带宽、访存容量、互联带宽同步大幅提升。

生态侧的同场数据也值得记录：CANN 外部开发者占比首次超过 61%、月活开发者 5200 人；910C 超节点部署已超 1000 套。

4. 竞争坐标：单卡有代差，系统级对打​

把 960DT 放到 2027 年的棋盘上看：

• 对 NVIDIA Rubin（R200：288GB HBM4 / 50 PFLOPS FP4）：单卡 FP4 算力约为 R200 的 8%（4 vs 50 PFLOPS），单卡代差客观存在；但 4096 卡超节点 + NPO 互联是系统级竞争——用"可交付的超大集群"对打单卡性能；
• 对采购方：960 的价值主张是"在国产量产约束内拿到最大可用集群"。DeepSeek 拟采购 16 万颗 950DT 跑推理的订单已经证明：当供给与生态到位，头部实验室愿意主动选国产；
• 对国产链条：950→960 的显存翻倍直接拉动国产 HBM 迭代，这是整条链的胜负手。

5. 小结​

• 960DT：FP8 2P / FP4 4P、288GB HBM、9.6TB/s，2027 Q2 上市，提前三个季度；
• 960 超节点：全球首个 NPO 超节点，4096 卡 / 8 EFLOPS FP8 / 1PB HBM / RTT 2μs；
• 路线图：一年一代官宣至 2029，950、960 均提前兑现，规划可信度显著上升；
• 看什么：2027 Q2 实际交付节奏、国产 HBM 产能、CANN 生态的第三方模型覆盖度。

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相关阅读​

• 昇腾 960 规格页（本站，含双版本与超节点完整参数）
• 国产三强 2026 H2：国产化率突破 40% 向 60% 迈进（已按 960 官宣更新）
• 2026 H2 AI 芯片路线图重大更新（已按 960 官宣更新）
• 昇腾 950 超节点 Q4 上市，中兴、新华三、曙光全线跟进

参考资料​

• 华为官网：发布全球首个采用 NPO 的超节点（昇腾 960 超节点）（2026-09-17）
• 电子工程专辑：国产 AI 芯片新突破！华为昇腾 960 芯片将提前发布
• 环球网：华为全联接大会 2026 主题演讲报道

本文基于华为官网新闻稿与公开报道整理。MFU、时延等收益数据为华为实验室仿真口径；2028 / 2029 产品仅为路线图官宣，规格以未来发布为准。

本周（2026 年 9 月 1 日–5 日）AI 算力行业的题眼，是两条相反方向的成本重构：海外，英伟达以史上最大并购吞下开发者生态入口，同时给旗舰减配显存——"内存太贵"倒逼硬件从单卡堆料走向系统级互联；国内，DeepSeek 16 万颗昇腾订单把"国产替代"从口号变成头部实验室的资产负债表决策，字节近 300 亿美元融资为算力扩张装上杠杆。

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1. DeepSeek 拟购 16 万颗昇腾 950DT：国产算力的"标志性订单"​

彭博社 9 月 4 日报道，DeepSeek 计划在内蒙古乌兰察布新建的约 1GW 数据中心部署至少 16 万颗华为昇腾 950DT，主要用于推理而非训练。按每颗约 11.1 万元的市场价估算，订单总额约 178 亿元人民币（约 25.6 亿美元）——这是迄今已知规模最大的昇腾集群，是半年前深圳首个万卡级集群的 16 倍。

三个关键读数：

• 主动选择，而非被迫替代：DeepSeek 是公认最会"榨干"算力的实验室。创始人梁文锋 7 月曾直言：华为超节点能完成 GB300 的任务、延迟没有明显差别，但约需 4 颗昇腾才抵 1 颗英伟达、技术上落后约两年。选择昇腾跑推理，是在综合成本、供应链安全与本土化后的理性决策——推理对软件生态依赖较浅，正是国产芯片的突破口；
• 瓶颈在供给端：受高端内存（HBM）短缺制约，昇腾 950DT 今年产量仅数十万颗（2026 年全部昇腾 die 计划约 160 万颗），DeepSeek 希望加购更多但产能所限，整单交付或需一年以上——国产 HBM 与先进封装成为整条链的胜负手；
• 过渡性押注：DeepSeek 同时在与中芯国际合作开发自研推理芯片，并于 6 月完成约 500 亿元融资、继续洽谈数十亿美元基建融资。国产算力的终局是多元自主，而非单一依赖。

单颗 950DT：144GB HBM、4.0TB/s 带宽、2.0TB/s 互联，原生支持 FP8/FP4/HiF8，详见昇腾 950DT 规格页。

2. 英伟达 129.3 亿美元收购 Hugging Face：买下"铲子的交易所"​

当地时间 9 月 3 日，英伟达宣布以 129.3 亿美元收购全球最大开源 AI 平台 Hugging Face，超过 2020 年 69 亿美元收购 Mellanox，成为其史上最大并购。交易含约 119 亿美元股权款与最高约 10 亿美元员工留任计划，预计 2027 年上半年完成，待监管批准。

Hugging Face 托管超 300 万个模型、50 万个数据集，服务超 1800 万名开发者。黄仁勋承诺平台继续开放中立运营：不强制绑定英伟达资源、开源属性完整保留。

解读：算力霸主的护城河从"芯片 + 网络 + 软件栈"一路修到了"模型分发 + 开发者生态"——卖铲人开始收购铲子的交易所。平台的"中立性"承诺能否兑现，将成为全球监管与竞争性云厂商持续盯防的焦点；对国内产业而言，模型托管、权重分发这类"轻资产 AI 基础设施"与芯片一样，正在成为大国科技博弈的卡点。

3. Rubin Ultra 显存减配：内存占 TCO 40% 后的算术题​

SemiAnalysis 最新报告（科创板日报 9 月 3 日转引）显示，英伟达已将旗舰 Rubin Ultra 的 HBM 配置从 HBM4E 12-Hi（384GB 档）下调至 HBM4 8-Hi（192GB），三星正配合开发 8 层产品。

• 动因：HBM/DRAM 涨价后，内存已占整机 TCO 约 40%；减配后 HBM 成本降超 50%，即便计入 2026 年 HBM 涨价预期，内存占总资本开支比例也将从 40% 压至 28%；
• 钱去了哪：转向 Scale-up 纵向扩展网络——以 NVL576 NPO 方案测算，光模块取代机架间互连后，Scale-up 网络占机架总支出比例从 4% 升至 12%；
• 连锁反应：TrendForce 显示英伟达自 2026 Q3 起并行评估 HBM4E 8-Hi / 12-Hi / HBM4 8-Hi 多套方案，部分云厂商也在考虑下调下一代自研 ASIC 的 HBM 容量。

连定价权最强的英伟达都给旗舰"减配求量"，等于官宣：当前 AI 硬件最紧的约束是内存（美光高管称新增内存供应 2028 年前难有实质放量），单卡堆料的军备竞赛告一段落，硬件价值重心正迁移到光互联、CPO、高速交换与 PTFE 背板。华泰测算 2027 年存储供需缺口将从约 -7% 收窄至 -3%——上行周期未逆转，但从"普涨"走向"结构性紧缺"。

详见本站已同步更新的 Rubin Ultra 规格页与HBM4 量产竞速分析。

4. 推理 ASIC 军备提速：谷歌"一年两款"，Jalapeño 规格落地​

• 谷歌 TPU 迭代周期从两年一代压缩至"每年两款"（华创证券 9 月 4 日研报）：第八代已拆分为训练（8t）与推理（8i）双架构，8i 把内存/算力配比拉到 8t 的 1.65 倍，专为推理放量设计；
• OpenAI Jalapeño 规格披露：6 堆栈 HBM4 共 216GB、带宽 15.4TB/s、700W，围绕投机解码设计；OpenAI 称在 DeepSeek R1 负载下 tokens/kW 达 GB300 的 1.7 倍；RTL 冻结到流片 9 个月，首批硅片后约 10 周承载 ChatGPT 流量。详见规格页（本站已更新）；
• workload-specific 时代开场：训练、推理、推荐各自长出专用芯片，上游 HBM/封装/光互联的供应节奏必须跟上"半年一代"。

5. 国内动态：字节 296 亿美元加杠杆，摩尔线程 Token 超节点投产​

• 字节跳动获约 296 亿美元融资安排（彭博 9 月 3 日），较最初约 200 亿美元目标大幅上调，用于数据中心与 AI 基建；另据产业报道正洽谈在内蒙古新增 5-6GW 算力产能——中国 AI 公司迄今最大规模基建融资之一，算力正被当作可融资、可证券化的重资产经营；
• 摩尔线程 × 趋境科技 "Token 超节点"投产（光明网 9 月 4 日）：以 MTT S500 承担 Prefill 与 KV Cache 生成、高带宽 GPU 专注 Decode 的 PD 异构方案，实测平均生成速度超 50 TPS、KV Cache 命中率超 90%、稳定性 99.9%，已承接头部模型厂商官方业务流量——超节点竞争维度从"单卡参数"转向"单位 Token 生产成本"；
• OpenAI 发布 GPT-6 Astra（9 月 4 日）：超 10 万颗 GPU 在 Stargate 集群完成训练，推理放量与超大规模集群仍是全球算力叙事主线；
• SemiAnalysis 基准：AMD MI355X 新提交在 AgentX 基准低交互区间tokens/$ TCO 击败 B300——vLLM + LMCache 软件栈的贡献首次被独立机构量化认可。

6. 市场：中美算力资产一涨一调​

美东 9 月 4 日，美国 8 月非农仅增 8.9 万人（预期 16 万），10 年期美债收益率回落至 3.78%，成长股走强：科技板块 XLK 周涨 4.2%，英伟达周涨 8.7% 收于 230.36 美元。A股 9 月 4 日反向回调：AI 算力芯片板块 -1.99%、服务器 -2.51%、超节点 -2.86%，浪潮信息跌停、寒武纪 -2.54%——基本面无恶化（博通、戴尔、中际旭创订单与财报持续验证景气），更多是交易层面获利兑现。

下周起三连催化密集：CIOE 光博会（9/9-11）→ 华为全联接大会（9/17-19）→ 云栖大会（9/22-24）。国产超节点从"发布会 PPT"到"批量交付"的成色，将迎来集中检验。

本周一句话​

内存太贵改变了所有人的算法：英伟达给旗舰减配显存、把钱投给互联；DeepSeek 用 16 万颗昇腾买推理确定性；谷歌把 TPU 迭代压到半年一代。2026 年 Q4 起，"每兆瓦/每美元 token 数"将取代"单卡 PFLOPS"，成为算力采购的第一指标。

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相关链接​

• 华为昇腾 950DT 规格页
• NVIDIA Rubin Ultra 规格页
• OpenAI Jalapeño 规格页
• NVIDIA Rubin 规格页

参考资料​

• 彭博社（转引）：DeepSeek 拟部署 16 万颗昇腾 950DT（2026-09-04）
• cnBeta/今日头条：DeepSeek 据称采购 16 万颗华为昇腾 950DT 芯片（2026-09-05）
• 科创板日报：SemiAnalysis 拆解 Rubin Ultra 减配（2026-09-03）
• Natural News/DailyAI：Nvidia To Acquire Hugging Face For $12.9B（2026-09-05）
• 光明网：摩尔线程 × 趋境科技 PD 异构推理方案投产（2026-09-04）
• AGI Hunt：AI News Daily 2026-09-05

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本文基于彭博社、科创板日报、SemiAnalysis、TrendForce、华创证券研报及光明网等公开报道整理。订单金额与市场数据为媒体/机构预估口径，实际以相关公司正式披露为准。

芯片追不上，系统来补。这是国产算力过去一年最清晰的战略共识。2026 年下半年，国产超节点正式从"概念发布"进入"产品密集发布、联合适配和商业部署"阶段：华为 Atlas 950 SuperPoD 真机已亮相并计划 Q4 上市，中兴、新华三、中科曙光、壁仞、沐曦等一众厂商相继入局。

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1. 华为 Atlas 950：业界最大 1024 卡超节点，Q4 上市​

继 7 月 WAIC 2026 真机首秀后，华为昇腾 950 超节点的商用脚步持续加快。核心规格：

指标	Atlas 950 SuperPoD
互联规模	最大 1024 × 昇腾 950DT（灵衢高速互联）
AI 算力	1 EFLOPS FP8/mxFP8/HiF8、2 EFLOPS FP4
全局内存	256TB 统一编址，片上内存最大 1024 × 96GB @ 4.0TB/s
互联带宽	单柜最大 64 × 1.68 TB/s（双向），3μs 超低 RTT
形态	满配 128 计算柜 + 32 互联柜，占地约 1000㎡，8192 颗 950DT
供电散热	全液冷，100kW 供电，380V AC/336V DC/240V DC
上市时间	2026 年第四季度

在 WAIC 展台之外，两个数字更能说明商业化进度：昇腾 384 超节点已商用落地 750 多套，规模应用于互联网、运营商、金融、教育、医疗等行业，并且是国内唯一训练出 SOTA 模型的超节点；更远期规划中，Atlas 950 SuperCluster（超 50 万颗昇腾芯片）同样定于 2026 Q4，Atlas 960 SuperPoD（15488 卡）与 Atlas 960 SuperCluster（超 100 万卡）将于 2027 Q4 接力。

华为的路线图背后是"Tau Scaling Law"——在 EUV 光刻机受限的前提下，通过系统级扩展突破单芯片物理极限，并计划到 2031 年将晶体管密度推升至 1.4nm 级工艺水平。

2. 超节点赛道全面开花：三条技术路线​

WAIC 之后，国产超节点形成了三类清晰的技术路线：

第一类：华为全栈自研。 同时掌握昇腾芯片、灵衢互联、Atlas 硬件、CANN 软件栈和 MindSpore 框架。CANN 已全面开源：社区上线 67 个项目、开源代码超 1244 万行、月活开发者突破 3500 人；昇腾开发者总数超 400 万。

第二类：中兴、新华三的兼容路线。 中兴发布 OEX 超节点新品，依托协议标准化与接口统一，全面兼容多元 GPU 生态；新华三 UniPoD S80000 系列可从 32 卡扩展至 1024 卡、最大支持 16384 卡互联，将 Scale-up/Scale-out 网络、液冷、供电、管理和故障恢复整合进同一套架构。

第三类：国产 GPU 联合创新。 中兴联合曦智、壁仞、沐曦、燧原、天数智芯等，基于 OEX+dOCS 架构打造国产高性能 Matrix 超节点；壁仞计划发布 BR20x 系列 GPU，基于自研 BLink 2.0 互联协议实现单超节点 1024 卡 Scale-up；沐曦推出"曦景"S 系列超节点。

在更大的 Scale-out 层面，中科曙光"曙光 8000（登峰）"全国产十万卡 AI 超集群已落成并接入国家超算互联网——它不是单体超节点，而是由大量计算节点、超节点和网络存储组成的超集群，检验的是国产算力的大规模调度、应用适配和工程交付能力。

3. 为什么"超节点"成了国产算力的主战场​

根本原因在于衡量标准变了：国产算力的评价体系，正从"比较单颗芯片的峰值性能"转为"一整套系统能够调动多少有效算力"。华为副董事长徐直军对此直言：单芯片上英伟达仍领先且短期难以追赶，但在超节点和集群层面，华为有信心。

这一转向的产业逻辑：

• 出口管制下的现实选择：单卡制程受限 → 用高速互联把更多 NPU 组织成一台"大计算机"；
• 需求侧真实拉动：万亿参数 MoE 模型的训练与推理，天然需要大规模低时延互联，超节点恰是对症下药；
• 生态护城河前移：CANN 开源 + MindSpore 兼容 PyTorch，把 CUDA 生态的竞争从"算子覆盖"层面拉回到"开发者规模"层面。

东兴证券指出，全球超节点赛道已聚集微软、Meta、亚马逊、三大运营商、阿里、字节、腾讯、百度、曙光、中兴、浪潮、新华三、海光、沐曦等数十家厂商——格局未定，但英伟达一家独大的局面正在被谷歌 TPU、AMD Helios、华为 Atlas 三股力量同时挑战。

4. 三道关卡：从"造出来"到"卖得动"​

业内人士普遍认为，国产超节点距离真正成熟还有三道坎：

1. 单芯片性能与单柜算力密度：受制程限制，单卡性能差距仍存，现阶段靠多柜互联和规模扩展另辟蹊径；
2. 规模扩展效率：超节点扩展到一定规模后性能提升边际递减，通信复杂度、能耗和容错成本持续上升；
3. 可验证的商业价值：下一阶段的比拼是有效算力利用率、单位 token 成本、模型适配广度与客户复购意愿。

一句话总结：2026 年是"中国超节点元年"，2027 年见真章——届时 Atlas 950 与 Vera Rubin NVL 系列将在全球两个平行市场各自接受规模化交付的检验。

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相关链接​

• 华为昇腾 950 规格页
• 华为昇腾 950DT 规格页
• 华为昇腾 910C 规格页

参考资料​

• 21 世纪经济报道：WAIC 上的算力重器——华为昇腾 950 超节点真机现身（2026-07-17）
• 昇腾社区：Atlas 950 SuperPoD 液冷超节点产品规格
• RCR Wireless：Huawei unveils new offering for AI infra at Shanghai event
• Seoul Economic Daily：Huawei Unveils Atlas 950 SuperPoD

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本文基于 WAIC 2026 现场报道、昇腾社区官方规格与公开研报整理。超节点性能数据均为厂商公布口径，独立第三方评测结果尚待观察。

August 23-25, 2026, the 38th Hot Chips (HC38) was held at Stanford's Memorial Auditorium. As the bellwether of global high-performance chip architecture, this conference landed exactly at the most intense moment of the AI compute arms race — the official agenda had 48 entries, including 7 AI accelerators, 6 memory tutorials, 6 CPUs, and 4 each of GPUs and networking. Putting the vendor talks together, one consensus emerged: the unit of AI compute competition has shifted from "single chip" to "whole rack / entire system."

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1. Overview: Three Days of Agenda, Almost a Preview of the 2027 AI Rack Market​

Monday (8/24) afternoon's GPU session was the focus, with four talks nearly colliding as the 2027 AI rack market:

• NVIDIA Rubin GPU ("Driving the Era of Agentic AI"): First chiplet-architecture GPU, 288GB HBM4, ~50 PFLOPS FP4, paired with 88-core Arm-architecture Vera CPU into NVL72 / NVL144 racks, mass production in H2 2026.
• AMD Instinct MI400 (two talks: architecture + system architecture): Told the "rack-scale" story thoroughly.
• Intel Crescent Island: A 350W air-cooled card designed for Agentic AI inference.

Tuesday (8/25) afternoon's AI session was almost a parade of "hyperscalers de-NVIDIA-izing": Google's 8th-gen TPU, OpenAI's first custom chip, Microsoft Maia 200, Meta MTIA, and Cerebras wafer-scale rack all appeared together.

Every vendor on stage used the term "Agentic AI" within the first two PPT slides — not a coincidence, but the collective shift in 2026 AI workload design goals.

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2. NVIDIA Rubin: One Rack Is a Supercomputer​

What NVIDIA featured at Hot Chips was not a single GPU but the Vera Rubin NVL72 whole cabinet — 72 Rubin GPUs + 36 Vera CPUs, 18 compute trays + 9 NVLink switch trays, about 1.3 million components, nearly 1,300 chips, weighing about 4,000 pounds (~1.8 tons).

The single Rubin GPU specs are equally stunning:

Metric	Rubin GPU	vs Blackwell
Transistors	336 billion (TSMC 3nm dual-die)	208 billion (+61.5%)
Memory	288GB HBM4	—
Bandwidth	22 TB/s	2.8× Blackwell
NVFP4 inference	50 PFLOPS	5× GB200
Training compute	35 PFLOPS	3.5×

The most disruptive design is in the compute tray: no cables, no hoses, no fans, all interconnected via the PCB backplane. NVIDIA says assembly time dropped from nearly 2 hours to 5 minutes (20× faster) while improving maintainability.

This time NVIDIA is selling not FLOPS but tokens per megawatt. Citing a SemiAnalysis benchmark based on DeepSeek-v4-PRO (140K+ context, AgentX workload), it claims: versus GB300 NVL72, Vera Rubin NVL72 delivers 10× to up to 30× tokens/MW as interaction intensity rises. A single cabinet provides 3.6 EFLOPS inference compute, whole-cabinet power 190-230kW; long-term capacity target is 1,000 NVL72 cabinets per day.

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3. AMD MI455X + Helios: Bigger Memory and Open Interconnect​

AMD's answer is the MI455X + Helios rack going head-to-head with NVIDIA. MI455X uses CDNA 5 architecture, 8 N2-process accelerator dies + N3P-process interconnect die, 256 workgroup processors, 192MB global L2.

Metric	MI455X	vs Rubin
Memory	432GB HBM4 (12-layer stack)	50% higher than Rubin's 288GB
Bandwidth	23.3 TB/s	Slightly ahead
MXFP4 compute	40.26 PFLOPS	—
System (Helios 72 cards)	2.9 ExaFLOPS FP4 inference	—
Price	~$5.25M per cabinet	—

At the system level, AMD bets on the UALoE (Ultra Accelerator Link over Ethernet) open standard: each GPU provides 3.6 TB/s bidirectional interconnect bandwidth; two 512-port 200G UALoE switch chips in the switch tray total 10.8 TB/s — opening the interconnect protocol to the whole industry while targeting NVLink.

Production cadence: AMD plans to deliver engineering samples and small-batch systems in H2 2026, with large-scale ramp in Q2 2027. Earlier rumors of Helios delay due to cooling issues were not confirmed by AMD.

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4. Intel Crescent Island: The Air-Cooled, Large-Memory "Cost-Effective Oddball"​

Intel offers a completely different path: Crescent Island — a 350W, air-cooled, standard-PCIe-slot inference GPU designed for Agentic AI, with the key metric being tokens per watt.

Metric	Crescent Island	Note
Architecture	Xe3P, 32 Xe cores, 32MB unified L2	Disclosed at Hot Chips
Memory	Intel branded card 160GB / ODM up to 480GB LPDDR5X	More than Rubin's 288GB HBM4
Form factor	350W air-cooled PCIe	Plugs into standard racks, no liquid-cooling retrofit
RAS	ECC, dynamic page offline, hard-package repair, PCIe advanced error reporting	Addresses "silent data corruption"

Intel's logic is clear: inference scenarios need far more memory capacity than bandwidth; using low-cost LPDDR5X for capacity and air cooling to skip liquid-cooling infrastructure drives down per-token cost. Combined with Diamond Rapids Xeon (256 performance cores, 1.28GB cache, 128 PCIe Gen6 lanes), Intel tries to surround from edge to datacenter with "CPU + inference GPU + open software stack."

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5. Custom ASIC Parade: Google, OpenAI, Microsoft, Meta Together​

Tuesday afternoon's AI session was the most historic of the conference — a parade of "hyperscalers de-NVIDIA-izing":

Chip	Vendor / Partner	Positioning	Key Specs / Progress
TPU 8t (Sunfish)	Google × Broadcom	Training	9,600 cards per pod, 121 FP4 ExaFLOPS, 2PB shared HBM
TPU 8i (Zebrafish)	Google × MediaTek	Inference	288GB HBM, 384MB on-chip SRAM (3× prev gen), ICI 19.2 Tb/s
Jalapeño	OpenAI × Broadcom	Inference	9-month end-to-end design, target ~50% token cost cut, commercial end of 2026
Maia 200	Microsoft (TSMC 3nm)	Inference	140B+ transistors, 10+ PFLOPS FP4, 216GB HBM3E, serving GPT-5.2 at Des Moines datacenter
MTIA 300-500	Meta (RISC-V) × Broadcom	Training + inference	Up to 25× compute gain, one model every 6 months before 2027

Google split TPU into training (8t) and inference (8i) dedicated architectures for the first time — its biggest architectural shift in a decade. Norm Jouppi personally took the stage to present TPU v8.

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6. Two Hidden Threads — Memory and Networking: HBM4 Year 1 + AI Factory OS​

Beyond GPUs/ASICs, two hidden threads mattered equally:

• Memory: Samsung's HBM Base Die (logic-process base die) and SK hynix's advanced packaging appeared together; the HBM4-era "base-die foundry" industry shift begins; HBF (high-bandwidth flash), LPDDR5X-PIM, 3D DRAM, and CXL compute-storage showcased "compute-in-memory" moving from papers to products.
• Networking: NVIDIA BlueField-4 (DPU) and Spectrum-X Multiplane architecture (presented by Gilad Shainer) — networking is becoming the decisive architecture for gigascale AI, scaling from hundreds of thousands to a million cards; Broadcom Thor Ultra Ethernet NIC keeps pressing; Mojo Vision showed chip-level optical I/O.

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7. Three Routes, One Consensus​

At the same conference, three vendors offered three distinctly different AI compute delivery philosophies:

1. NVIDIA: Full-stack closed integration — GPU, CPU, DPU, and switch chips all self-designed, pushing system performance to the extreme via ultimate software-hardware co-design, at the cost of deep customer lock-in.
2. AMD: Open-standard catch-up — Uses larger HBM4 capacity + UALoE open interconnect for a "cost-effective + open" play, tearing open the inference gap with Meta and OpenAI's 12GW-class orders.
3. Intel: Air-cooled cost-effectiveness — Abandons liquid cooling and HBM, uses LPDDR5X large memory + standard PCIe, betting that "most inference doesn't need a 200kW rack."

But all three agree: the unit of competition is no longer the chip, but the co-designed system (rack / system). For buyers, 2027 compute planning should compare not "single-card PFLOPS" but "tokens per megawatt, latency, availability, and full-lifecycle cost."

Related Links​

• NVIDIA Rubin spec page
• AMD MI455X spec page
• Intel Crescent Island spec page
• Google TPU 8t spec page
• Google TPU 8i spec page

References​

• Hot Chips 2026 Three Giants Together: Rubin 336B Transistors, MI455X 432GB, Crescent Island 480GB - IC Chip Industry Watch
• Hot Chips Day 2: Rubin, MI400 and Diamond Rapids Go Head-to-Head - AI2Work
• NVIDIA Vera Rubin NVL72 Rack at Hot Chips 2026 - ServeTheHome
• Hot Chips 2026: 4 Hyperscalers Put Custom AI Silicon on One Afternoon - Sean Kim

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This article is compiled from Hot Chips 2026 (Aug 23-25) official presentations and on-site reports from ServeTheHome, SemiAnalysis, TechPowerUp, etc. Performance data are vendor-disclosed figures; actual performance subject to mass-produced products.

In 2026, China's AI chip market landscape has shifted from "NVIDIA unipolar dominance" to "overseas vendors leading, domestic multi-route catch-up." According to industry research, China's overall AI accelerator market was ~4M units in 2025, of which 1.65M were domestic, with share first breaking 40%; as products iterate and fabs follow up, the localization rate is expected to rise to 60%-70% by 2027. This article focuses on the latest H2 2026 progress of Huawei Ascend, Cambricon, and Moore Threads — the domestic "Big Three."

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1. Huawei Ascend: 950 Capacity Fully Booked, 960 Roadmap Unveiled​

Ascend's core advantage is "architecture + full-stack ecosystem synergy," with ~800K units shipped in 2025, capturing 50% of the total domestic vendor share. The product iteration cadence is clear:

Time	Product	Note
2025 Q1	Ascend 910C	Main transitional model
2026 Q1	Ascend 950PR	Inference flagship
2026 Q4 (planned)	Ascend 950DT	Training flagship, drives domestic HBM iteration
2027-2028	Ascend 960 / 970	Roadmap products

950 series capacity has entered a "fully booked" state: 950PR entered mass production in April 2026; June monthly capacity jumped to 500K-600K units (nearly 10x MoM), with a full-year target of 1.2M units at 100% certainty; ByteDance locked in 350K units for $5.6B, while Tencent / Alibaba / Baidu combined locked in 400K units.

Ascend 960 roadmap specs (per roadmap disclosure):

Metric	Ascend 960
Architecture	Ascend 6th gen (Da Vinci v6)
FP8 compute	~4 PFLOPS
Memory	288GB
Memory bandwidth	9.6 TB/s
Super-node	Atlas 960 SuperPoD, 15,488 cards, Lingqu optical-electrical converged bus
Debut	2027 Q4 (roadmap)

The previous-gen Ascend 384 super-node has cumulatively shipped over 750 sets, deployed across 20+ industries including internet, operators, finance, education, and healthcare — Huawei calls it "the only domestic super-node that has trained a SOTA model."

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2. Cambricon MLU690: H2 Mass Production, Entering ByteDance Bidding Window​

Cambricon is the core domestic compute leader in the absence of an Ascend IPO, with the technology gap continuously narrowing:

• Siyuan 590 (7nm): Performance equivalent to 80% of A100, already supports DeepSeek, continuously adapting to mainstream large models like Qwen 3 and GLM
• Siyuan 690 series: Will enter mass production in H2 2026, expected to achieve order scale-up during ByteDance's H2 bidding window
• Revenue certainty: Equity incentive targets show >100% revenue growth for the next 3 years: 2026 revenue target 13.5B RMB, 2027 27B RMB, 2028 60B RMB

Cambricon fully benefits from the industry dividend of "domestic CSP capex + full adaptation of domestic large models and domestic chips," making it the most direct elasticity play on rising localization rate.

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3. Moore Threads MTT S5000: Full-Function GPU + Ecosystem Breakthrough​

Moore Threads takes a differentiated "full-function GPU" route, with the flagship MTT S5000 based on the 4th-gen "Pinghu" MUSA architecture:

Metric	MTT S5000
Dense AI compute	1000 TFLOPS
Memory	80GB
Memory bandwidth	1.6 TB/s
Inter-card interconnect	784 GB/s
Precision	FP8 to FP64 full precision (training + inference)
Security	First batch to pass national "Safe and Reliable Evaluation" (Level I)

Its engineering capability is verified: the Kuae (KUAE) intelligent computing cluster based on S5000 achieves 95% training linear scaling efficiency, with compute efficiency loss within 5% at ten-thousand-card scale; supports checkpoint-resume training with effective training time ratio >90%; and has trained a MoE-236B base model with >25 trillion tokens of corpus from scratch.

The ecosystem is Moore Threads' deepest moat: MUSA has achieved 100% core math library compatibility, 3000+ PyTorch operator compatibility, covers 55 categories of core AI operators, has official vLLM and SGLang support, Day-0 adaptation of mainstream models, and 800K+ developers. Its PD heterogeneous-disaggregation solution achieves equivalent replacement of international high-end GPUs at a 2:1 ratio with S5000, significantly reducing inference cost.

The 5th-gen "Huagang" architecture (released 2025-12) supports FP4 to FP64 full precision, with 50% higher compute density and 10x better energy efficiency than the previous gen, supporting 100K+ card clusters; cumulative R&D investment in the "Huashan" (train-infer integrated) and "Lushan" (graphics rendering) new chips based on this architecture exceeds 900M RMB.

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4. Software Ecosystem Decides: Day-0 Adaptation Becomes Routine​

Beyond hardware, software ecosystem realization is the watershed for domestic compute in 2026:

• Huawei's CANN heterogeneous computing architecture and MindSeries suite are fully open-sourced, with the community incubating 67 projects, 12.44M+ lines of code, and 3,500+ monthly active developers
• The "release-and-adapt" closed loop between domestic large models and domestic chips has basically formed: Tencent Hunyuan T3 (295B), DeepSeek-V4, and GLM-5.2 all completed Day-0 adaptation
• 2026 is regarded as the "first year of domestic super-nodes"; Huatai Securities estimates China's super-node architecture market will reach 341.4B RMB by 2028, with a 2026-2028 CAGR of 194%

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5. Industry Judgment: From "Can It Be Built" to "Can It Be Used Well"​

The domestic Big Three are converging along three paths:

1. Huawei: Locks government/enterprise and internet big customers with super-node system-level capability + full-stack software
2. Cambricon: Impacts the revenue inflection point by narrowing the training-side gap + scaling up via big-customer bidding
3. Moore Threads: Covers cloud-edge-end full scenarios with full-function GPU generality + mature CUDA-compatible ecosystem

The common shortcoming of all three remains advanced process and HBM supply — precisely the core link of overseas controls. But as domestic HBM iterates and fabs follow up, a realistic path to 60%-70% localization by 2027 exists.

Related Links​

• Huawei Ascend 960 spec page
• Huawei Ascend 950DT spec page
• Cambricon MLU690 spec page
• Moore Threads MTT S5000 spec page

References​

• Domestic AI Chip Industry View Update - Robo Datayes
• Moore Threads, Two Positives in One Day - Eastmoney
• Moore Threads × SiliconFlow: PD Disaggregation Heterogeneous Compute Co-location Whitepaper - EE Focus
• After Approaching Break-even, Moore Threads Faces Hong Kong "Big Exam" Again - Top News

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This article is compiled from public industry research, broker views, and corporate announcements as of August 2026. Some shipment and market-share figures are third-party estimates, not officially confirmed data.

The 2026 World Artificial Intelligence Conference (WAIC) was held July 17-20, 2026 at the Shanghai World Expo Center, themed "Intelligent Partners, Creating the Future Together." Over 1,100 companies showcased 3,000+ exhibits, with 300+ products debuting globally. For the compute-card industry, this concentrated review of domestic compute sent a clear signal: the competitive main line is shifting from "single-chip peak compute" to "SuperNode system-level effective compute."

1. Huawei Atlas 950 SuperPoD: live debut, wins SAIL grand award​

Huawei's Atlas 950 SuperPoD live hardware made its first public appearance at WAIC 2026, on-site carrying 16 compute cabinets with 1,024 Ascend cards total. With three system-level innovations — "ultra-wide bandwidth, ultra-low latency, unified memory addressing" — it stood out from hundreds of domestic and international entries to win the conference's top honor, the SAIL (Super AI Leader) Award.

Core parameters (confirmed on-site at WAIC)​

Metric	Atlas 950 SuperPoD
Exhibited scale	16 compute cabinets / 1,024 Ascend cards
Max interconnect scale	8,192 Ascend NPU cards fully interconnected (full config)
Interconnect protocol	Huawei in-house "Lingqu" (UnifiedBus) 2.0
Total compute	1 EFLOPS FP8 / 2 EFLOPS FP4 (1,024 cards); full 8,192-card ~8 EFLOPS FP8
Unified memory	256 TB globally unified memory address space
Interconnect latency	3 μs ultra-low RTT; TB-level NPU interconnect bandwidth
Full config	128 compute cabinets + 32 interconnect cabinets = 160 cabinets, ~1000㎡, carrying 8,192 Ascend 950DT
Launch	Full config planned for Q4 2026
Cooling	Fully liquid-cooled blind-plug architecture

Huawei disclosed for the first time: the previous-gen Ascend 384 SuperNode has cumulatively shipped 750+ units commercially, deployed across 20+ industries including internet, operators, finance, education, healthcare, transportation, and manufacturing, calling it "the only domestic SuperNode that has trained SOTA models."

2. Software ecosystem: CANN fully open-sourced, developers at scale​

Beyond hardware, Huawei highlighted open-source software ecosystem progress:

• CANN heterogeneous compute architecture and MindSeries base software suite were fully open-sourced end of 2025;
• The CANN open-source community has incubated 67 projects, 12.44M+ lines of code, with 3,500+ monthly active developers;
• Huawei has co-developed 7,000+ solutions with 3,000+ industry partners, serving 2,000+ core government/enterprise customers;
• WAIC showcased 60+ real business scenarios, 20+ benchmark cases, covering the full chain from technology breakthrough to scaled commercial deployment.

3. Domestic chips' Day-0 adaptation becomes routine​

On July 6, 2026, Tencent released the MoE model Hunyuan T3 (295B parameters, 256K context); domestic chips rapidly completed Day-0 adaptation:

Vendor	Chip	Adaptation status
Moore Threads	MTT S5000	Completed rapid Hunyuan T3 adaptation (previously adapted DeepSeek-V4, GLM-5.2)
MetaX	Xiyun C series	In-house MXMACA stack first to full-chain Day-0 adaptation, zero-code deployment

Moore Threads also showcased the MTT C256 SuperNode (first-of-its-kind single-layer Scale-up 256-card full interconnect, sub-microsecond latency) and three AI-factory solutions — "model training factory / token production factory / agent production factory."

4. More domestic compute debut highlights​

Vendor / product	Highlight
Orient AlphaChip DF1000	World's first "software-defined + near-memory computing" 3D chip, interconnect pitch compressed to sub-micron
ZhongHao XinYing "Xuyu"	Fully in-house next-gen TPU-architecture AI-specific chip, with Taize 2.0 server
Enflame × Iluvatar	Domestic high-performance Matrix SuperNode based on OEX+dOCS architecture, shortlisted for the conference "Excellent AI Leader Award"
Rongming Microelectronics	Advancing next-gen VPU, evolving from video processing to "visual-agent compute base"

The domestic AI chip lineup also included Moore Threads, MetaX, Enflame, Houmo, Cixiong, Suaneng, SemiDrive, Phytium, Aixin, Iluvatar, and others.

Industry interpretation: from "can it be built" to "is it used well"​

WAIC 2026 reflects a fundamental shift in the competitive stage of domestic AI chips:

1. SuperNode becomes the main battlefield: beyond single-chip performance, system-level capabilities — "inter-chip interconnect + cluster scale + cooling" — become the breakthrough key. Huawei Lingqu and Enflame/Iluvatar OEX are both pushing here. Huatai Securities defines 2026 as the "first year of domestic SuperNodes," estimating China's SuperNode architecture market could reach ¥341.4B by 2028, with 2026-2028 CAGR of 194%.
2. Software ecosystem delivers: Day-0 adaptation has gone from slogan to routine; the "launch-and-adapt" closed loop between domestic large models (DeepSeek-V4, GLM-5.2, Hunyuan T3) and domestic chips is essentially formed.
3. Demand-side endorsement: China Mobile earlier released its 2026-2027 AI SuperNode centralized procurement announcement — about 6,208 cards, over ¥2B — accelerating domestic SuperNode scaled commercialization.

Related links​

• Huawei Ascend 950DT specs
• Huawei Ascend 950PR specs
• Moore Threads MTT S5000 specs

References​

• Ascend 950 SuperNode live at WAIC 2026, wins SAIL top award - Global Times
• 2026 WAIC compute competition enters "system-level" battlefield, Ascend 950 SuperNode debuts - Tencent News
• Huawei unveils advanced Atlas 950 SuperPoD - China Daily
• Huawei Ascend 950 wins WAIC 2026 SAIL top honor - Huxiu
• Compute heavyweights at WAIC: Huawei Ascend 950 SuperNode live - 21st Century Business Herald

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This article is compiled from WAIC 2026 (July 17-20) on-site and official disclosures, and will continuously track the 950 SuperNode Q4 launch.

The Ascend 950 series (950PR inference / 950DT training) has become the core supply of domestic AI compute. Per multiple brokerages and industry research, 950 series capacity is 100% booked with scarce spot supply; the full-year 1.2M-unit target is "100% certain," with expectations of an upward revision to 1.5M. This article summarizes capacity and order data as of July 2026.

1. Capacity pace: ~10× MoM jump in June​

Time	950PR monthly capacity	Notes
May 2026	50k-60k units	Near full production
June 2026	500k-600k units	~10× MoM; SMIC, Hua Hong tier-1 suppliers on overtime
Q3 2026 (est.)	700k-800k units	Per month
Full-year 2026 target	1.2M units	Upward revision to 1.5M expected

Supply chain delivery is tight: high-speed backplanes and liquid-cooling connectors' lead time stretched from 2 weeks to 6-8 weeks; orders are booked into 2027.

2. Order structure: top cloud providers + operators + overseas​

Customer	Locked volume	Amount / Notes
ByteDance	350k 950PR	$5.6B, concentrated delivery from Q3 2026
Tencent / Alibaba / Baidu	~250k 950PR + 150k 950DT	Combined ~400k units
Three major operators	200k+ units	Centralized procurement, for intelligent compute centers and AI private networks
Overseas	South Korea 2,000 units, Malaysia 3,000 servers, Russia ten-thousand-card cluster	From pilot to commercial

3. Shipment forecast: firmly #1 domestic​

Per CCA (Kezhi) Consulting estimates:

Metric	2025	2026 (forecast)
Huawei Ascend total shipments	812k cards	1.026M cards
Of which 950PR	—	~800k units
Of which 950DT	—	~100k-200k units

Huawei has completed the product transition from the 910 series to the 950 series. The internet industry has become Ascend's largest application market; competitive advantage is extending from single-hardware performance to software ecosystem and system capabilities.

4. Going overseas: formal South Korea entry in Q4​

Per Korean media ETNews, Huawei plans Q4 2026 to formally enter the South Korean market with the Ascend series and Atlas 950 SuperPod:

• Local distributor agreements signed; two channel partners including SK Shieldus selected
• Main products: 950PR (mass-produced and delivered since April) and 950DT (launched Q4)
• Official line: 950PR inference performance is 2.87× that of H20, priced at about 1/4 of it

5. WAIC 2026: 1024-card live debut confirmed​

At WAIC 2026 (July 17-20, Shanghai), Huawei's Atlas 950 SuperPoD live hardware made its first public appearance — a 16 compute-cabinet, 1,024 Ascend-card scale — and won the conference's top honor, the SAIL Award:

• Core metrics: total compute 1 EFLOPS FP8 / 2 EFLOPS FP4, 256 TB globally unified memory addressing, Lingqu 2.0 interconnect, 3 μs ultra-low RTT latency
• Full configuration: 128 compute cabinets + 32 interconnect cabinets = 160 cabinets, ~1000㎡ footprint, carrying 8,192 Ascend 950DT, planned Q4 2026 launch
• Commercial foundation: previous-gen 384 SuperNode has cumulatively shipped 750+ units, deployed in 20+ industries
• Software ecosystem: CANN fully open-sourced end of 2025; community incubated 67 projects, 12.44M+ lines of code, 3,500+ monthly active developers

WAIC's debut confirmed the 950 series' "SuperNode-first" product logic: beyond single-card compute, system-level effective compute (interconnect bandwidth + unified memory + low latency) is the key dimension for domestic compute to benchmark against international flagships.

Ascend roadmap recap​

Product	Positioning	Key metrics (official roadmap)
950PR	Inference	1 PFLOPS (FP8) / 2 PFLOPS (FP4), 2 TB/s interconnect
950DT	Training	SuperNode core, launched Q4
960	Train/inference	2 PFLOPS (FP8) / 4 PFLOPS
970	Next-gen	In planning

Industry interpretation​

1. Domestic substitution moves from inference to training: 950PR (inference) ramps first, 950DT (training) follows in Q4, combined with the Atlas 950 SuperPoD ten-thousand-card interconnect — domestic compute now has the complete "training substitution" puzzle for the first time.
2. Capacity is the biggest variable: order certainty is extremely high, but SMIC/Hua Hong advanced-process capacity, HBM supply, and advanced packaging remain ramp bottlenecks — the root of "scarce spot supply."
3. Going overseas opens a second growth curve: bulk procurement from South Korea, Malaysia, Russia, and Latin America marks domestic compute's shift from "internal circulation" to "external circulation."

Related links​

• Huawei Ascend 950PR specs
• Huawei Ascend 950DT specs
• Huawei Ascend 950 specs

References​

• China intelligent-compute chip competitive landscape (CCA data) - IDCquan
• Ascend 950 series capacity and orders - Eastmoney
• WAIC catalyst: Huawei Ascend 950 SuperNode live debut - 10jqka
• Huawei Ascend 950 enters South Korea in Q4: 2.87× H20 inference - Toutiao

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Data in this article is based on official and major brokerage research; capacity/orders are dynamic figures and will be continuously updated.

In the first half of 2026, the AI chip industry underwent a historic turning point — the center of gravity shifted from the "training race" to "inference efficiency," domestic chip market share broke 40% for the first time, NVIDIA built higher barriers with Blackwell Ultra, and the inference-specific chip track bloomed in diversity.

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I. Compute Doubles Again: NVIDIA Blackwell Ultra Launch (June 1)​

On June 1, 2026, NVIDIA CEO Jensen Huang unveiled the new-generation AI chip Blackwell Ultra at Computex 2026 (Taipei), setting a new starting line for the AI infrastructure race over the next two years.

Key Specs​

Metric	Blackwell Ultra	B200	Improvement
FP8 compute	20 petaFLOPS	~10 petaFLOPS	100%
Architecture	Blackwell Ultra	Blackwell	Upgrade
Expected delivery	2027 Q1	2026 Q1	—
Positioning	Hyperscale training + inference	Training + inference	Flagship

Industry Significance​

1. Direct impact of doubled compute: 20 petaFLOPS FP8 means training time for hundred-billion-parameter models drops sharply; trillion-parameter model training moves from "scientific experiment" to "engineering routine"
2. System-level balance: Blackwell Ultra is not just a chip but a system-level engineering breakthrough across NVLink, HBM, cooling, and power delivery
3. Roadmap certainty: The Q1 2027 delivery timeline lets cloud vendors and AI labs plan infrastructure budgets 18 months ahead

Challenges​

• Energy crisis: Doubled performance comes with sharply higher power; datacenter power and cooling design face extreme challenges
• Accessibility: Top-tier compute goes first to top cloud vendors; how smaller developers and research institutes reach compute at reasonable cost via cloud services
• Software stack adaptation: New hardware needs matching CUDA versions and framework support; software ecosystem maturity becomes the key bottleneck for compute conversion

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II. Domestic AI Chips: The Tipping Point from "Usable" to "Good"​

On June 16, 2026, Xinchuang World published "2026 China Domestic AI Chip Vendor Capability Quadrant", clearly outlining the overall domestic landscape.

2.1 Capability Quadrant Ranking​

Quadrant	Representative Vendors
Leader quadrant	Huawei Ascend, Hygon, Cambricon, Alibaba T-Head, Moore Threads
Visionary quadrant	Baidu Kunlunxin, Biren, Enflame, Iluvatar, HardyVision
Contender quadrant	TSINGMICRO, Black Sesame, SemiDrive, Lisuan, Houmo
Challenger quadrant	Denglin, Zhicun, VeriSilicon, Rockchip, Intellifusion

2.2 Huawei Ascend: The Anchor of Domestic Compute​

Market Position​

• In 2025, Ascend series shipped 812,000 units, capturing 49% of the domestic AI accelerator card share, firmly No.1 domestically
• Ascend 950PR single-card FP8 compute reaches 1P (PetaFLOPS), FP4 compute reaches 2P
• Inference performance is about 2.87x that of NVIDIA H20, priced at only 72,000-75,000 RMB, a significant price/performance advantage

Full-Stack Advantage​

Huawei's "device-network-cloud-chip" integrated strategy is Ascend's core moat:

• Chip design: Da Vinci 3.0 architecture iterating continuously
• OS: HarmonyOS/Euler OS deeply optimized
• Networking: Euler network protocol stack
• Cloud: Huawei Cloud ModelArts platform seamlessly integrated

Latest Progress​

• On June 5, 2026, Shenzhen Hetao College, together with HIT (Shenzhen) and Huawei, completed full-parameter post-training of a 1.6-trillion-parameter DeepSeek V4 Pro model on an Ascend 910C cluster
• This is the first time domestic AI chips completed trillion-parameter-level model training, marking "domestic substitution" moving from inference to training

2.3 Cambricon: The First Profitable Domestic AI Chip Benchmark​

Performance Explosion​

Metric	Full-year 2025	2026 Q1	YoY Growth
Revenue	6.497B RMB	2.885B RMB	+453% / +160%
Net profit	2.059B RMB (first annual profit)	1.013B RMB	— / +185%

Core Product: Siyuan 590​

• In DeepSeek R1 inference scenarios, TPS reaches 942, about 50% higher than H20
• Years of joint optimization with ByteDance; strongest short-term cloud inference deployment capability
• Of 2.885B RMB Q1 2026 revenue, Siyuan 590 contributed over 70%

Potential Risks​

Absent from the 2nd 2026 "Safe and Reliable Evaluation Results Announcement"; the reason is unclear and will affect its domestic government/enterprise market performance.

2.4 TSINGMICRO: The "Third Route" of Reconfigurable Chips​

Technical Route​

TSINGMICRO adopts a reconfigurable dataflow architecture同源 with Groq LPU, finding a balance between GPU generality and ASIC extreme efficiency.

Metric	TSINGMICRO TX81	Traditional GPU	Advantage
Inference cost	Baseline	+100%	Reduced 50%
Energy efficiency	Baseline	Baseline	3x improvement
Architecture	Reconfigurable dataflow	SIMT/SIMD	Better for inference

Deployment Progress​

• Cumulative shipments of reconfigurable chips exceed 30 million units
• Scaled deployment in a dozen-plus thousand-card-scale intelligent computing centers nationwide
• Has begun A-share IPO tutoring; likely to become the "first reconfigurable chip stock"

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III. The Inference Chip Track: Core Signal of the Industry Shift​

On June 4, 2026, TrendForce published a deep report "The Era of Inference Economy: The Rules of AI Chips Are Being Rewritten," pointing out that the compute competition center of gravity is shifting from training to inference.

3.1 Why Now?​

Cost Structure Changed​

• Training is a one-time cost: Once a model is trained, marginal cost approaches zero
• Inference is a recurring cost: Every API call, every generated token represents compute consumption and gross-margin pressure
• Per-unit inference cost and energy efficiency directly affect gross margin and scale-expansion capability

Model Compression Tech Matured​

• 1.58-bit quantization and weight pruning let models maintain inference accuracy at extremely low memory footprint
• MoE (Mixture of Experts) architecture activates only a few expert sub-networks per inference via "partial wake-up," greatly reducing actual computation
• The rise of slimmed models provides commercial viability for hard-wired inference chips

3.2 NVIDIA's $20B Bet: Acquiring Groq (December 2025)​

On December 24, 2025, NVIDIA acquired Groq's inference technology license and core team for $20 billion, one of NVIDIA's largest M&A/tech acquisitions ever.

Strategic intent:

1. Fill the inference gap: NVIDIA GPU is unshakable in training, but inference efficiency was never its strongest suit
2. Counter specialized inference chips: Cerebras, Taalas, SambaNova and other startups are eroding the inference market
3. Position for Agentic AI: Agentic AI needs extremely low-latency, high-throughput inference

3.3 Taalas HC1: Proof of Concept for Hard-Wired Inference​

On February 20, 2026, Canadian AI chip startup Taalas launched inference chip Taalas HC1, directly etching Meta's open-source AI model Llama 3.1 8B into the chip.

Key Metrics​

Metric	Taalas HC1	NVIDIA B200 (throughput optimized)	Advantage
Inference rate	16,960 tokens/s/user	Baseline	~4-5x
Cost per million tokens	0.75 cents	3.79 cents	Reduced 80%
Power	~250W	~700W	Reduced 64%
Process	TSMC N6	TSMC 4nm	More mature
HBM	❌ Not used	✅ HBM3e	Lower cost

Technical Principle​

Taalas HC1 uses an aggressive Computing-in-Memory (CIM) implementation:

• Model weights directly固化 in Mask ROM (fully hardware-defined)
• On-chip SRAM handles dynamic data (KV cache and LoRA fine-tuning weights)
• Only 2 mask layers need modification to produce a dedicated chip for another AI model; turning an AI model into a physical chip takes only 2 months

Limitations​

• Lack of flexibility: Hard-wiring cannot cope with rapidly iterating model updates
• Ecosystem barrier: The current cloud market still relies on general-purpose platforms; customers may prefer flexible solutions that upgrade with models
• NRE cost: High one-time engineering cost, requiring sufficient deployment scale to amortize

3.4 Cerebras: The IPO Path of Wafer-Scale Integration​

On May 14, 2026, Cerebras Systems officially listed on NASDAQ, becoming the first wafer-scale AI chip company to go public.

Core Technology: Wafer-Scale Integration (WSI)​

• WSE-3 (third-gen wafer-scale engine): An entire 12-inch wafer as a single chip
• 44GB on-chip SRAM: No external HBM, eliminating the memory bandwidth bottleneck
• 21 PB/s bandwidth: On-chip communication bandwidth, thousands of times that of GPUs
• Partnership with OpenAI: Signed a 3-year, 750MW, $20B+ compute cooperation agreement

IPO Significance​

Cerebras's listing marks the maturation of the inference-specific chip track:

1. Capital markets begin pricing such companies
2. Proves "non-GPU" technical routes have commercial viability
3. Provides valuation references for other inference chip startups (Groq, SambaNova, Taalas, etc.)

3.5 Inference Chip Landscape: Multiple Technical Routes Coexist​

Company	Technical Route	Core Advantage	Representative Product
Taalas	Hard-wired (Mask ROM)	Extreme inference efficiency, low cost	HC1
Cerebras	Wafer-scale integration (WSI)	Ultra-high bandwidth, large-model inference	WSE-3
Groq	SRAM-first architecture	Deterministic latency, high throughput	LPU (acquired by NVIDIA)
d-Matrix	Digital in-memory compute (DIMC)	More flexible than hard-wiring	Corsair
Etched	Hard-wired Transformer	Works for all Transformer models	Sohu
Axelera AI	Digital in-memory compute (D-IMC) + RISC-V	High energy efficiency	Metis AIPU

TrendForce predicts:

• General-purpose GPUs still dominate training and multi-model environments
• But in mature, predictable scenarios, general-purpose GPU profit margins will be compressed
• The industry shifts from general compute monopoly to a dual-track structure of general + specialized coexistence

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IV. Overall Domestic AI Chip Landscape in H1 2026​

4.1 Industry Enters Scale-Up Phase​

Metric	2025	2026 Q1	Trend
Domestic AI accelerator shipments	1.65M units (41% share)	—	Rising
Total China AI accelerator shipments	~4M units	—	—
Hygon revenue growth	—	Doubled	↑
Cambricon revenue growth	—	+160%	↑
Moore Threads revenue growth	—	Doubled	↑

Leading vendors collectively entered the revenue realization channel, moving from "technical validation" to "scale commercialization."

4.2 Three Core Development Trends​

Trend 1: Capitalization Wave Reshapes the Landscape​

• Late 2025 to early 2026: Moore Threads, Iluvatar listed on the STAR Market
• Biren listed on the Hong Kong stock exchange
• Enflame STAR Market IPO accepted
• Kunlunxin, T-Head initiated listing processes
• TSINGMICRO, HardyVision and others advancing IPOs

Capitalization brings dual effects:

• ✅ Positive: Supports R&D and ecosystem building
• ⚠️ Negative: Valuation bubbles and revenue realization pressure

Trend 2: Capacity Becomes the Biggest Constraint Variable​

The contradiction between explosive domestic AI chip demand and limited advanced-process capacity is sharpening:

Vendor	Advanced-process capacity need	Actually obtained
Huawei Ascend	15K wafers/month (7nm-class)	Priority guaranteed
SMIC total capacity	~20K wafers/month (7nm-class)	—
Other vendors	~5K wafers/month combined	Extremely tight

Whether stable wafer capacity can be secured directly determines vendor survival. Cambricon's 75.4% inventory-to-revenue ratio is essentially a lock on capacity.

Trend 3: Competition Shifts from "Usable" to "Good"​

Early competition focused on "can it run the model"; now it's about "runtime efficiency, deployment cost":

Dimension	"Usable" era	"Good" era
Hardware performance	Can it run the model	Runtime efficiency, energy efficiency
Software stack	Basic adaptation	Maturity, framework breadth
Ecosystem	Existence	Developer community activity
Deployment cost	Insensitive	Core competitive factor

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V. H2 2026 Outlook​

5.1 Upcoming Key Events​

Time	Event	Impact
2026 Q3	NVIDIA Rubin architecture details revealed	Next-gen flagship specs unveiled
2026 Q3	Huawei Ascend 950PR/950DT formally launched	New benchmark for domestic inference chips
2026 Q4	AMD MI350X scaled delivery	NVIDIA Blackwell competitor
2026 Q4	Cambricon Siyuan 690 launch (est.)	New-gen training chip
2027 Q1	NVIDIA Blackwell Ultra delivery	New compute benchmark lands

5.2 Key Competitive Factors Over the Next Three Years​

1. Wafer capacity access: Advanced-process capacity is a scarce resource; vendors tied to SMIC and TSMC have inherent advantages
2. Capital operation efficiency: The IPO window is limited; raising enough capital on the market determines R&D sustainability
3. Software ecosystem depth: Hardware performance is only the entry ticket; software stack maturity, framework adaptation breadth, and developer community activity are the core moat

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VI. Conclusion: A Diverse Ecosystem Will Eventually Form​

In H1 2026, the AI chip industry is undergoing a historic transition from "one dominant player" to "pluralistic coexistence."

• NVIDIA builds higher training barriers with Blackwell Ultra while laying out inference efficiency via the Groq acquisition
• Huawei Ascend holds the domestic compute baseline with full-stack capability; 950PR begins to surpass H20 in inference
• Cambricon proves the commercial viability of domestic AI chips by turning profitable first; Siyuan 590 surpasses international rivals in specific scenarios
• Cerebras, Taalas and other inference-specific chip companies opened a "non-GPU" third route
• TSINGMICRO's reconfigurable architecture provides a diversified technical route choice for China's AI chips

Over the next three years, the domestic AI chip endgame will form a pluralistic ecosystem where GPU, ASIC, and reconfigurable computing three technical routes coexist, with cloud and edge developing in coordination. "Domestic substitution" is no longer a slogan, but an industrial reality happening now.

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Data sources:

• Xinchuang World "2026 China Domestic AI Chip Vendor Capability Quadrant" (2026-06-16)
• TrendForce "The Era of Inference Economy: The Rules of AI Chips Are Being Rewritten" (2026-06-04)
• RayByte "Compute Doubles! NVIDIA Blackwell Ultra Chip Launched" (2026-06-02)
• Official financial reports and announcements of each company

Related reading:

• Huawei Ascend 910C Specs Deep Dive
• Full Comparison Table

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