AI Compute Cards Wiki Editorial

On June 5, 2026, Shenzhen announced a major piece of news: Shenzhen Hetao College, together with HIT (Shenzhen) and Huawei, used 1,000 Huawei Ascend 910C chips to successfully complete full-parameter post-training of the 1.6-trillion-parameter DeepSeek-V4-Pro large model.

This was no tentative attempt, but a milestone technological breakthrough. It proved with irrefutable engineering results that: domestic AI chips are fully capable of supporting world-class, super-large-parameter model training.

Why this matters​

The two thresholds of AI chips: "inference" and "training"​

• Inference: using an existing model to chat, write copy. Domestic chips could already do this
• Training: adjusting model parameters to learn new capabilities. Full-parameter training adjusts all 1.6 trillion parameters at once — maximum difficulty

Previously, full-parameter training of trillion-scale models was monopolized by NVIDIA H100/H200. Domestic chips could only do inference, not large-scale training.

The significance of this breakthrough: domestic compute leapt from "usable" to "useful", from "inference" to "training".

Technical details​

Training configuration​

Item	Parameter
Chips	Huawei Ascend 910C × 1,000
Model	DeepSeek-V4-Pro
Parameters	1.6 trillion (1600B)
Training type	Full-parameter post-training
Framework	MindSpore + torch_npu
Completed	Announced June 5, 2026

Performance metrics​

Metric	Value	Assessment
Compute utilization	>30%	Industrial grade (top overseas chips ~40%)
Key training operator efficiency	+14%	vs previous-gen 910B
Communication bandwidth utilization	>60% (est.)	MoE All-to-All communication
Stability	1,000 cards trained continuously with no failures	Cluster stability met standard

💡 About 30% compute utilization: many feel 30% is low, but in large-model training this is already a very respectable industrial-grade level. Even with the most advanced overseas chips, many teams' actual utilization is around 40%.

Ascend 910C detailed specs​

Ascend 910C is Huawei's AI training/inference chip announced at the Huawei Analyst Conference (April 24, 2024), with a theoretical peak of 800 TFLOPS (BF16), in the same class as NVIDIA H100.

Parameter	Ascend 910C	Ascend 910B	NVIDIA H100
Architecture	Ascend 910C	Ascend 910B	Hopper
Process	TSMC 7nm (est.)	TSMC 7nm	TSMC 4NP
BF16 compute	800 TFLOPS	256 TFLOPS	989 TFLOPS (sparse)
Memory	64GB HBM (est.)	64GB HBM2e (B1/B2)	80GB HBM3
Memory bandwidth	~2TB/s (est.)	600 GB/s (B1/B2)	3.35 TB/s
TDP	~400W (est.)	300-400W	700W
Mass production	April 2026 (full production)	Nov 2022	Mar 2022

Key upgrades:

• ✅ 3× compute: from 910B's 256 TFLOPS to 800 TFLOPS
• ✅ Mature software ecosystem: torch_npu adapts PyTorch, MindSpore framework mature
• ✅ Cluster stability: 1,000 cards trained continuously with no failures (the biggest breakthrough)

Technical challenges and solutions​

Challenge 1: Memory demand of trillion-scale models​

A 1.6-trillion-parameter model needs, just for model parameters:

• FP16: 1.6T × 2 bytes = 3.2 TB
• Plus gradients and optimizer states: at least 10 TB of memory

Huawei's solution:

• Model Parallel: distribute the model across 1,000 910C chips
• ZeRO optimizer: optimize memory footprint
• Gradient accumulation: update parameters in stages

Challenge 2: Communication efficiency of thousand-card clusters​

Training with 1,000 chips, inter-chip communication becomes the bottleneck. MoE models need All-to-All communication (each expert may need to communicate with all others).

Huawei's solution:

• HCCS (Huawei Collective Communication Scheduler): in-house high-speed interconnect protocol
• Layered communication: intra-node NVLink + inter-node HCCS
• Communication-compute overlap: data transfer concurrent with computation

Challenge 3: Training stability​

Trillion-scale model training takes weeks or months; any single card failure can interrupt the entire training.

Huawei's solution:

• Fault detection and auto-recovery: real-time monitoring of card status, auto-restart and recovery on failure
• Checkpoint optimization: high-frequency training-state saves (every N steps)
• Ascend cluster management software: designed specifically for enterprise training

Competitive comparison​

Vendor	Chip	1.6T-param training	Ecosystem maturity	Availability
Huawei	Ascend 910C	✅ Completed	⭐⭐⭐ (improving)	China-localized
NVIDIA	H100/H200	✅ Industry standard	⭐⭐⭐⭐⭐	Global (export-controlled)
AMD	MI300X	✅ Feasible	⭐⭐⭐⭐	Global
Google	TPU v5p/8t	✅ JAX-native	⭐⭐⭐⭐	Google Cloud

Conclusion: Ascend 910C has caught up to H100 in hardware performance, still lags in software ecosystem, but this training success proves engineering feasibility.

Industry impact​

1. The "Zunyi Conference" of domestic compute​

This breakthrough is called the "Zunyi Conference" of domestic compute — from passive defense to strategic counteroffensive.

Specific impact:

• ✅ Breaks the bias that "domestic chips can only do inference"
• ✅ Proves domestic chips can train frontier models
• ✅ Provides compute foundation for domestic large models (e.g., DeepSeek-V4, ERNIE 5.0)

2. Impact on NVIDIA​

Huawei Ascend 910C completing trillion-scale training means China's AI industry is less dependent on NVIDIA.

Scenario	Before	Now
Inference	Domestic chips usable	Domestic chips useful
Training	Must use H100/H200	Can use 910C
Large-scale training	Must use H100 clusters	Can use 910C clusters

3. Boost to the domestic chip industry​

This breakthrough will drive the entire domestic AI chip supply chain:

• Chip design: Cambricon, MetaX, Moore Threads accelerate iteration
• Wafer manufacturing: SMIC, Hua Hong get more orders
• Packaging/test: JCET, TFME benefit

Huawei Ascend roadmap (2025-2028)​

Time	Chip	Positioning
Q1 2025	Ascend 910C	Flagship training/inference (mass-produced)
Q1 2026	Ascend 950PR	Inference-optimized (~500 TFLOPS BF16)
Q4 2026	Ascend 950DT	Data-center training
Q4 2027	Ascend 960	Next-gen flagship
Q4 2028	Ascend 970	Next-next-gen

Training lessons shared​

The Shenzhen Hetao College team accumulated valuable experience:

✅ Successes​

1. Progressive training: start from small models (7B), gradually scale to 1.6T
2. Mixed-precision training: BF16 main + FP32 gradient accumulation
3. Communication optimization: All-to-All overlap with computation
4. Fault recovery: save checkpoint every 1,000 steps

⚠️ Challenges encountered​

1. Memory fragmentation: severe fragmentation over long training, needs periodic cleanup
2. Communication bottleneck: MoE All-to-All takes 30%+ of training time
3. Software bugs: torch_npu occasional memory leak, needs training process restart

Related chips​

• Huawei Ascend 910C - the chip used in this training
• Huawei Ascend 910B - previous-gen chip
• Huawei Ascend 950PR - next-gen inference chip
• NVIDIA H100 - benchmark product
• NVIDIA H200 - benchmark product (HBM3e upgrade)

References​

• Sina Finance: Huawei Ascend 910C completes DS-V4-Pro training
• Tencent News: Milestone! Ascend 910C completes 1.6-trillion-param model training
• 21IC: Huawei chip completes full-parameter post-training of 1.6T AI model

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This article is compiled from public reports. Salute to the teams at Shenzhen Hetao College, HIT (Shenzhen), and Huawei — you proved the feasibility of China's AI compute with engineering results.

On March 18, 2026, Intel officially launched at the Intel AI Summit: the Habana Gaudi 4 custom AI accelerator. This is Intel's latest-gen AI training/inference chip after Gaudi 3 (launched April 2024), designed for large-scale model training.

Meanwhile, Intel confirmed its next-gen Jaguar Shores GPU (datacenter GPU) is in development, will use HBM4 memory, and is expected in 2027. This marks Intel's formal return to the AI chip race.

Key Highlights​

• Gaudi 4: Launched March 2026, TSMC 5nm, 64GB HBM3e, for large-scale training
• Jaguar Shores: Launches 2027 (est.), HBM4, targeting NVIDIA Rubin
• Crescent Island: Intel's first general-purpose GPU (launched 2026), Xe3 architecture
• Software ecosystem: Intel AI Stack (including oneAPI, BigDL, Gaudi Software Suite)
• Foundry partners: TSMC (Gaudi 4, Jaguar Shores), Intel Foundry (Crescent Island)

Gaudi 4 Detailed Specs​

Gaudi 4 is the fourth-gen AI accelerator designed by Intel's Habana Labs (acquired 2019).

Parameter	Gaudi 4	Gaudi 3 (2024)	NVIDIA B200
Architecture	Habana 4	Habana 3	Blackwell
Process	TSMC 5nm	TSMC 7nm	TSMC 4NP
FP8 compute	~2,000 TFLOPS (est.)	1,000 TFLOPS	4,500 TFLOPS (sparse)
Memory	64GB HBM3e	128GB HBM2e (est.)	192GB HBM3e
Memory bandwidth	~3 TB/s (est.)	~2 TB/s (est.)	8 TB/s
TDP	~500W (est.)	~400W	700-1000W
Interconnect	RoCE v3 (Ethernet)	RoCE v2	NVLink 5.0
Launch	March 2026	April 2024	March 2024
Mass production	2026 Q3 (est.)	Q4 2024	Q4 2024

📌 Note: Gaudi 4 exact specs not fully public; some values above are estimates.

Gaudi 4 Key Features​

1. Native Ethernet support: Uses RoCE v3 (RDMA over Converged Ethernet), no dedicated interconnect protocol needed (like NVLink)
2. Large-scale scaling optimized: Ten-thousand-card cluster scaling efficiency better than InfiniBand (lower cost)
3. Sparsity acceleration: Native MoE model support
4. Multi-precision support: FP8/FP16/FP32/INT8/INT4
5. Open ecosystem: Supports PyTorch, TensorFlow, JAX (via third-party adaptation)

Jaguar Shores: Intel's Next-Gen GPU​

Jaguar Shores is Intel's first true datacenter GPU (not an ASIC like Gaudi).

Why "Jaguar Shores"?​

• Jaguar: Symbolizes "speed" and "agility"
• Shores: Symbolizes "openness" and "connection"

Jaguar Shores Estimated Specs​

Parameter	Jaguar Shores (est.)	NVIDIA Rubin	AMD MI455X
Architecture	Xeu 3 (est.)	Rubin	CDNA 4
Process	TSMC 3nm (est.)	TSMC 3nm	TSMC 3nm
Memory	HBM4 (confirmed)	HBM4	HBM4
Memory capacity	288GB (est.)	288GB	288GB
FP8 compute	~4,000 TFLOPS (est.)	~6,000 TFLOPS	6,000 TFLOPS
TDP	~800W (est.)	~1,000W	~800W
Launch	2027 (est.)	2026 Q3	2026 Q3

Key confirmations:

• ✅ HBM4 memory: Intel confirmed Jaguar Shores will use SK hynix HBM4
• ✅ TSMC foundry: Jaguar Shores will be produced by TSMC (not Intel Foundry)
• ✅ oneAPI native support: Jaguar Shores will natively support the oneAPI programming model

Crescent Island: Intel's First General-Purpose GPU​

Crescent Island is Intel's first general-purpose datacenter GPU announced October 2025, using the Xe3 architecture (upgrade of Xe-HPG).

Parameter	Crescent Island (est.)	Intel Data Center GPU Max	NVIDIA L40S
Architecture	Xeu 3	Xeu 2 (Ponte Vecchio)	Ada Lovelace
Positioning	General compute + AI inference	HPC + AI training	AI inference + graphics
Process	TSMC 5nm (est.)	Intel 7 + TSMC 5nm	TSMC 4N
Memory	48GB HBM3 (est.)	128GB HBM2e	48GB GDDR6
TDP	~300W (est.)	600W	350W
Launch	2026 (est.)	Jan 2023	Mar 2023

Positioning:

• ✅ General-purpose GPU: Both AI inference and scientific computing (HPC)
• ✅ Low cost: Cheaper than Gaudi 4, targeting NVIDIA L40S
• ✅ Open standards: Supports oneAPI, SYCL, Level Zero

Intel AI Chip Roadmap (2024-2027)​

Time	Product	Type	Process	Note
2024 Q4	Gaudi 3	AI ASIC	TSMC 7nm	Current mainstay
2026 Q2	Crescent Island	General GPU	TSMC 5nm	New launch
2026 Q3	Gaudi 4	AI ASIC	TSMC 5nm	New launch
2027	Jaguar Shores	Datacenter GPU	TSMC 3nm	Next-gen flagship
2027	Gaudi 5 (est.)	AI ASIC	TSMC 3nm	Next-gen

vs Competitors​

Gaudi 4 vs NVIDIA B200​

Metric	Gaudi 4	NVIDIA B200
FP8 compute	~2,000 TFLOPS	4,500 TFLOPS
Memory	64GB HBM3e	192GB HBM3e
Interconnect	Ethernet (RoCE v3)	NVLink 5.0
Software ecosystem	Gaudi Software Suite	CUDA
Price	est. ~$20,000	~$45,000
Advantage	Low Ethernet cost, open	Most mature ecosystem, strongest performance
Disadvantage	Weak software ecosystem, lower compute	Expensive

Conclusion: Gaudi 4 is positioned as a "cost-effective training solution," suited for cost-sensitive customers willing to invest in software adaptation.

Jaguar Shores vs NVIDIA Rubin​

Metric	Jaguar Shores (est.)	NVIDIA Rubin
FP8 compute	~4,000 TFLOPS	~6,000 TFLOPS
Memory	288GB HBM4	288GB HBM4
Software ecosystem	oneAPI	CUDA
Mass production	2027	2026 Q3
Advantage	Open standards, possibly cheaper	Mature ecosystem, first-mover advantage
Disadvantage	Weak ecosystem, 1 year late	Expensive

Conclusion: If Jaguar Shores launches on time with sufficient oneAPI ecosystem improvement, it can become NVIDIA's third choice (after NVIDIA and AMD).

Software Ecosystem: oneAPI Progress and Challenges​

What is oneAPI?​

oneAPI is Intel's open, cross-architecture programming model:

• Supports CPU, GPU, FPGA, AI accelerators
• Based on SYCL standard (similar to CUDA's C++ extensions)
• Open-source implementation (Intel oneAPI Base Toolkit)

Intel AI Stack​

Component	Purpose	Counterpart
oneAPI	Cross-architecture programming model	CUDA
BigDL	Distributed deep learning framework	PyTorch Distributed
Gaudi Software Suite	Gaudi-specific software stack	NVIDIA GPU Cloud (NGC)
Intel Extension for PyTorch	PyTorch optimization on Intel hardware	NVIDIA PyTorch
Intel Optimization for TensorFlow	TensorFlow optimization on Intel hardware	NVIDIA TensorFlow

✅ Progress​

• PyTorch 2.5+: Intel Extension integrated into PyTorch mainline
• Hugging Face Transformers: Official Intel GPU support (via optimum-intel)
• vLLM: Experimental Gaudi support (performance TBD)

⚠️ Challenges​

• Developer habits: Global AI developers use CUDA; oneAPI has a steep learning curve
• Operator coverage: Many PyTorch operators lack oneAPI-optimized versions
• Performance: At same power, Gaudi 4 performance is only ~50% of B200

Industry Impact​

1. Can Intel Return to the AI Race?​

Challenges:

• ❌ Ecosystem disadvantage: CUDA moat too deep, oneAPI hard to shake
• ❌ Performance disadvantage: Gaudi 4 only ~50% of B200
• ❌ Timing disadvantage: Jaguar Shores 1 year later than Rubin

Opportunities:

• ✅ Open standards: Not dependent on CUDA, suited for "anti-NVIDIA-monopoly" customers
• ✅ Ethernet advantage: RoCE v3 cheaper than InfiniBand at ten-thousand-card scale
• ✅ Intel Foundry: If Jaguar Shores uses Intel's own process, lower cost

2. Impact on AMD​

Intel's return to the AI race is bad for AMD:

• AMD was the "only NVIDIA alternative"
• Now Intel is back too; AMD's "alternative" status is challenged
• But in the short term (2026-2027), Intel cannot yet threaten AMD

3. Impact on Domestic Chips​

Intel Gaudi 4's launch is a reference case for domestic chips:

• Proves the Ethernet route (RoCE) is viable
• Proves open ecosystem (oneAPI) is hard but necessary
• Proves the cost-effective route has a market (cost-sensitive customers)

Related Chips​

• Intel Gaudi 3 - Previous-gen product
• Intel Gaudi 4 - New launch (to be created)
• Intel Crescent Island - Intel's first general GPU (to be created)
• NVIDIA B200 - Direct competitor
• AMD MI455X - Same-gen competitor

References​

• Intel Newsroom: Gaudi 4 Launch
• Tom's Hardware: Intel Jaguar Shores to use HBM4
• Wccftech: Intel Next-Gen Jaguar Shores GPU
• U.S. News: Intel Signals Return to AI Race

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This article is compiled from Intel official announcements and public materials. Some specs are estimates, subject to final Intel release.

On June 1, 2026, NVIDIA founder and CEO Jensen Huang officially announced at COMPUTEX 2026 (Taipei) that: the Vera Rubin platform has entered full production. This marks a fundamental paradigm shift for AI hardware from "discrete accelerators" to "integrated AI factories."

Key Highlights​

• Rubin GPU: Next-gen AI compute chip, FP4 compute is 3.6× that of Blackwell
• Vera CPU: 88 custom Arm cores (176 threads), replacing the Grace CPU
• NVLink 6: GPU-to-GPU interconnect bandwidth reaches 260 TB/s (double Blackwell)
• CX8 SuperNIC: 800Gb/s network, ConnectX-9 link reaching 28.8 TB/s
• HBM4 memory: 288GB per chip, 13 TB/s bandwidth
• Agentic throughput: 10× over Grace Blackwell

Complete Vera Rubin Platform Specs​

Vera Rubin is not a single GPU but a complete AI factory platform comprising 7 chips:

Chip	Type	Purpose
Rubin GPU	Main AI compute chip	Training + inference
Rubin Ultra GPU	Flagship version	Ultra-scale inference
Vera CPU	CPU paired with Rubin	Host CPU + data preprocessing
NVLink 6	Interconnect chip	High-speed GPU interconnect (260 TB/s)
CX8 SuperNIC	NIC	800Gb/s network
XDR 800G switch	Datacenter network	Cross-rack communication
Rubin Platform POD	Whole cabinet	Pre-configured AI factory (144 GPUs)

Rubin GPU Detailed Specs (estimated)​

Parameter	Rubin GPU	Rubin Ultra	Blackwell (B200)
Architecture	Rubin	Rubin Ultra	Blackwell
Process	TSMC 3nm (est.)	TSMC 3nm	TSMC 4NP
Memory	288GB HBM4	288GB HBM4E (est.)	192GB HBM3e
Memory bandwidth	13 TB/s	13+ TB/s	8 TB/s
FP4 compute	~3,600 TFLOPS (est.)	~5,000 TFLOPS (est.)	2,250 TFLOPS
TDP	1,000W (est.)	1,200W (est.)	700-1000W
Interconnect	NVLink 6 (260 TB/s)	NVLink 6	NVLink 5 (1800 GB/s)
Mass production	2026 Q3	H2 2027	2024 Q4

📌 Note: Rubin's exact specs are not fully public yet; some values above are estimates.

Vera CPU: The New Host CPU Replacing Grace​

Vera CPU is NVIDIA's self-designed Arm-architecture CPU, replacing the previous Grace CPU:

Parameter	Vera CPU	Grace CPU
Cores	88 cores (176 threads)	72 cores (144 threads)
Architecture	Custom Armv9 (est.)	Arm Neoverse V2
Interface	NVLink 5.0 (1.8 TB/s)	NVLink 4.0 (900 GB/s)
TDP	~500W (est.)	350-500W
Purpose	AI factory Host CPU	HPC / AI Host

Key upgrade: Vera's co-design with the Rubin GPU achieves end-to-end optimization in compute, data loading, and preprocessing, comparable to Google TPU 8t's Arm Axion integration.

Performance vs Blackwell​

NVIDIA officially claims that under the same POD configuration (144 GPU chips):

Metric	Grace Blackwell (GB200 NVL72)	Vera Rubin NVL144	Improvement
FP4 compute	1.1 PFLOPS	3.6 PFLOPS	3.3×
Memory capacity	288GB×72 = 20.7TB	288GB×144 = 41.4TB	2×
Memory bandwidth	8 TB/s×72	13 TB/s×144	~3.3×
NVLink bandwidth	1800 GB/s×72	260 TB/s (full POD)	~2×
Agentic throughput	Baseline	10×	10×
Performance per watt	Baseline	25× (vs CPU alone)	25×

💡 Why "10× agentic throughput"? Agentic AI workloads differ from training/inference: one prompt may trigger multiple stages including reasoning, retrieval, tool calls, and response generation, involving thousands of steps. The Rubin platform is optimized for this long-chain, high-concurrency workload.

MGX Third-Gen Rack-Scale System​

Vera Rubin adopts the MGX third-gen open rack-scale system design:

• Five-rack synergy: Vera Rubin NVL72 system + Vera CPU + Groq 3 LPX + Vera BlueField-4 STX storage + Spectrum-6 SPX Ethernet
• Global supply chain: 30 countries, 350+ factories, hundreds of partners (Dell, HPE, Lenovo, Supermicro, Asus, Foxconn, etc.)
• Spectrum-X Ethernet silicon photonics: World's first switch based on CPO (co-packaged optics) supporting 200Gb/s SerDes, now in mass production

Mass Production Timeline​

Time	Event
Jan 2026	CES 2026 first unveils Rubin platform
June 1, 2026	COMPUTEX 2026 announces full production
Fall 2026	Vera Rubin officially starts mass production and shipment
H2 2027	Rubin Ultra launch (HBM4E upgrade)
2028	Feynman architecture (next gen)

AI Factory: From Selling Chips to Selling "Smart Production Lines"​

Huang said something at the launch that shook the industry:

"Rubin's Agentic AI throughput is 10× that of Blackwell. Rubin is a complete AI factory platform."

This marks a fundamental shift in NVIDIA's business model:

• Past: Sold GPUs (H100/B200), customers built systems themselves
• Now: Sells "complete AI factory solutions" (Vera Rubin POD), including GPU, CPU, network, storage, software stack
• Future: Becomes the "TSMC" of global AI infrastructure (providing smart production capacity)

vs Competitors​

Vendor	Product	Positioning	Advantage	Disadvantage
NVIDIA	Vera Rubin	Complete AI factory solution	Most complete ecosystem, most mature software	Expensive, extremely high power
AMD	MI455X (MI400 series)	Training competitor	Price/performance, open ecosystem	Software ecosystem gap
Google	TPU 8i/8t	Cloud training/inference	Deep Gemini integration	Google Cloud only
Huawei	Ascend 910C/950	Domestic substitution	China localization, AscendMind framework	Affected by export controls

Industry Impact​

1. AI labs: Frontier model training time shrinks from "months" to "weeks"
2. Cloud providers: Must decide whether to procure Vera Rubin POD (conflicts with self-developed chip strategy)
3. Hyperscale datacenters: AI factory becomes a new competitive dimension (whoever has the strongest compute can train the strongest model)
4. Domestic chips: Ascend 910C/950, Cambricon MLU590, etc. must catch up to Blackwell in 2026-2027, or the gap will widen to the Rubin era

Related Chips​

• NVIDIA Rubin R200 - Rubin architecture GPU detailed specs
• NVIDIA Vera CPU - Vera CPU detailed specs
• NVIDIA B200 - Previous-gen Blackwell architecture
• AMD MI455X - Direct competitor (MI400 series)

References​

• NVIDIA Blog: Vera Rubin Full Production
• COMPUTEX 2026 Keynote
• NVIDIA Official Newsroom

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This article is compiled from NVIDIA official announcements and public materials. Some specs are estimates, subject to final official release.

In 2026, China's domestic AI chip industry has entered a period of full-scale explosion. The three giants — Huawei Ascend, Baidu Kunlun, and Alibaba T-Head — have successively launched next-generation products, while Cambricon, MetaX, Enflame, and Iluvatar have also achieved important breakthroughs.

This article comprehensively analyzes 2026 domestic AI chip progress across four dimensions: product launches, technology breakthroughs, market dynamics, and ecosystem building.

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1. Huawei Ascend: 950 series launched, 960/970 roadmap clear​

1.1 Ascend 950PR (launched Q1 2026)​

Core specs:

Item	Parameter
Launch date	March 21, 2026
Platform	Atlas 350 accelerator card
HBM capacity	128 GB (Huawei in-house HiBL 1.0 HBM)
Memory bandwidth	1.6 TB/s
FP8 compute	1 PFLOPS
Positioning	Inference-specific (Prefill stage)
Performance vs.	Single-card compute is 2.87× NVIDIA H20

Technology innovations:

• First adoption of Huawei in-house HBM solution (HiBL 1.0), lowering cost
• Supports FP8 low-precision compute, 3× inference energy-efficiency improvement
• Optimized for inference scenarios such as video recommendation and real-time interaction

Commercialization progress:

• Mass supply began in Q1 2026
• Key customers: China Telecom, China Mobile, China Unicom, Huawei Cloud
• Priced around ¥100,000/card (¥80,000 for key accounts), ~30% lower than comparable competitors

1.2 Ascend 950DT (launched Q4 2026)​

Core specs:

Item	Parameter
Launch date	Q4 2026 (expected October)
HBM capacity	144 GB (Huawei in-house HiZQ 2.0 HBM)
Memory bandwidth	4 TB/s (HiZQ 2.0 technology)
FP8 compute	1 PFLOPS
Positioning	Inference + training (Decode stage + training tasks)
Technology innovation	First to carry in-house HiZQ 2.0 memory technology

Technology innovations:

• Adopts HiZQ 2.0 memory technology, 2× data-movement efficiency
• Supports FP8/FP4 low-precision compute, balancing performance and efficiency
• Optimized for scenarios such as dialogue generation and large-model training

1.3 950 SuperNode (launched Q4 2026)​

System specs:

Item	Configuration
Max interconnected chips	8,192 chips
Total FP8 compute	1 EFLOPS (1,024-card scale)
1024-card version	16 liquid-cooled cabinets, 64 chips per cabinet
Supported models	Trillion-parameter large-model training
Deployment progress	1,024-card version already in deployment

Performance comparison:

• 950 SuperNode outperforms NVIDIA's 2027 NVL576 system
• Leads by 20% in trillion-parameter model training

1.4 Ascend 960/970 roadmap​

Chip model	Launch	Core specs	Positioning
Ascend 960	Q4 2027	N+3 process, 288GB HBM, FP8 2 PFLOPS, 30%+ better energy efficiency than 910C	Ultra-large-scale training
Ascend 970	Q4 2028	N+3 process, FP4 8 PFLOPS, 4 TB/s bandwidth, supports trillion-parameter models	Next-gen AI architecture (MoE, etc.)

Technology breakthroughs:

• Process upgrade: from N+2 (7nm-class) to N+3 (5nm-class)
• Memory capacity doubled: from 144GB (950DT) to 288GB (960/970)
• Energy efficiency improved: 960/970 are 30%+ better than 910C
• Precision optimized: 970 supports FP4 precision, optimized for next-gen AI architectures (MoE, etc.)

1.5 Commercialization progress​

Shipment data:

• 384-card SuperNode: over 500 units deployed, the only truly large-scale commercial SuperNode in China
• 2026 shipment target: 800k chips (1M cumulative)
• Market share: 60% of China's AI chip market

Ecosystem building:

• CANN compiler: open-sourced end of 2025, seamless PyTorch/TensorFlow migration
• Mind series toolchains: fully open, lowering the developer barrier
• Ecosystem partners: over 3,000
• Developer community: over 500k registered developers

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2. Baidu Kunlun: M100 inference-specific, Tianchi SuperNode deployed​

2.1 Kunlun M100 (launched early 2026)​

Core specs:

Item	Parameter
Launch date	Early 2026 (expected Q2)
Positioning	Inference-specific
Architecture	In-house XPU-P architecture (inference-optimized)
Process	7nm (SMIC N+2)
HBM capacity	64 GB (inference-optimized)
TDP	250 W (low-power inference)
Performance vs.	1.5× P800 inference, 38% lower power

Technology innovations:

• Adopts RISC-V open instruction set, adding 50+ AI-specific instructions
• Compute per watt reaches 8.3 TOPS/W, 2.1× the industry average
• Supports models from 10 billion to 100 billion parameters for inference

Commercialization progress:

• Mass supply in Q2 2026
• Key customers: Baidu Smart Cloud, China Merchants Bank, Southern Grid, Geely Auto
• Priced around ¥60,000/card, clear cost-performance advantage

2.2 Kunlun M300 (launched early 2027)​

Core specs:

Item	Parameter
Launch date	Q1 2027 (expected March)
Positioning	Ultra-large-scale multimodal training
Architecture	In-house XPU-P architecture (multimodal-optimized)
Process	5nm (SMIC N+3)
HBM capacity	256 GB HBM4
TDP	500 W
Modalities	Text, images, video and other data types

Technology innovations:

• Adopts HBM4 memory, bandwidth up to 3.2 TB/s
• Supports FP8/FP4 low-precision compute, 2× training energy-efficiency
• Native support for multimodal model training (text + image + video)

2.3 Tianchi 256-card SuperNode (launched June 2026)​

System specs:

Item	Configuration
Launch date	June 2026 (expected)
Chip count	256 Kunlun P800/M100
Effective training rate	97%
Inter-chip bandwidth	1.2 TB/s
Validated models	Baidu ERNIE 5.1 and other key large models

Performance breakthroughs:

• Fully domestic SuperNode, fully autonomous and controllable from chip to network
• 97% effective training rate, surpassing NVIDIA DGX SuperPOD's 95%
• Training validation completed for Baidu ERNIE 5.1 and other key large models

2.4 Commercialization progress​

Shipment data:

• P800: 150k shipped in 2025, 200k target in 2026
• Ten-thousand-card clusters: multiple P800-based clusters delivered
• Market share: 20% of China's AI chip market

Customer coverage:

• External customer revenue share: over 50% in 2025
• China Mobile AI server procurement: P800-based bids won 70%, 70%, 100% shares
• Key customers: China Merchants Bank, Southern Grid, Geely Auto, iFlytek

IPO progress:

• May 2026: officially launched STAR Market IPO tutoring
• Plans "A+H" model — simultaneous A-share and Hong Kong listings
• Valuation exceeds ¥10 billion

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3. Alibaba T-Head: M890 3× performance, Zhenwu series ships 560k units​

3.1 T-Head M890 (launched Q2 2026)​

Core specs:

Item	Parameter
Launch date	Q2 2026 (Alibaba Cloud Summit)
Performance	3× previous generation
HBM capacity	144 GB
Inter-chip bandwidth	800 GB/s
Precision support	FP8, FP4 low-precision compute
Positioning	Full training + inference pipeline

Technology innovations:

• Adopts in-house ICN inter-chip protocol, inter-chip latency under 150 ns
• Companion PCCF communication library and ICN Switch chip enable full-bandwidth interconnect of 64 chips within a single node
• Supports FP8/FP4 low-precision compute, balancing performance and efficiency

3.2 T-Head V900 (launched Q3 2027)​

Core specs:

Item	Parameter
Launch date	Q3 2027 (expected September)
Performance	3× again over M890
HBM capacity	216 GB
Inter-chip bandwidth	1,200 GB/s
Positioning	Ultra-large-scale training

3.3 T-Head G900 (launched Q3 2028)​

Core specs:

Item	Parameter
Launch date	Q3 2028 (expected September)
Positioning	Flagship product for next-gen compute demand
Technology innovation	Supports full-pipeline training of trillion-parameter models

3.4 Zhenwu series commercialization progress​

Shipment data:

• Cumulative shipments: over 560k units as of April 2026
• Customers served: 20+ industries, 400+ customers
• Autonomous driving: over 130k units, 30+ customers
• Finance: over 100k units, 150+ customers

Performance advantage:

• At equal precision, Zhenwu series single-machine inference outperforms comparable products by 50%+ on average
• Panjiu server SuperNode architecture supports trillion-parameter large models on a single node

Full product line:

• Zhenwu series AI chips: training + inference
• Yitian series CPUs: data center CPUs
• ICN Switch interconnect chip: inter-chip interconnect
• Camel920 400G smart NIC: high-speed networking
• Junyue series storage controller chips: storage optimization

---

4. Other domestic chip vendor progress​

4.1 Cambricon MLU590 (launched Q1 2026)​

Core specs:

Item	Parameter
Launch date	Q1 2026 (expected March)
Architecture	MLUarch 09 (in-house)
Process	7nm (SMIC N+2)
HBM capacity	128 GB HBM3
TDP	350 W
Positioning	Training + inference

Technology innovations:

• MLUarch 09 architecture, 2× compute over MLU590
• Supports FP8/FP4 low-precision compute, 2.5× inference energy-efficiency
• Native MoE architecture support, 3× sparse-model inference efficiency

Commercialization progress:

• Q1 2026: sample deliveries begun
• Key customers: Chinese government, state-owned enterprises, research institutes
• Day-0 adaptation of DeepSeek-V3 671B achieved

4.2 MetaX Xiyun C600 (launched Q2 2026)​

Core specs:

Item	Parameter
Launch date	Q2 2026 (expected June)
Architecture	MXMACA 3.0 (CUDA-compatible)
Process	7nm (SMIC N+2)
HBM capacity	128 GB HBM3
TDP	350 W
Positioning	Training + inference

Technology innovations:

• MXMACA 3.0 architecture, CUDA-compatible, low migration cost
• Supports FP8/FP4 low-precision compute, 2× training energy-efficiency
• Fully domestic supply chain, autonomous and controllable from chip to packaging

Commercialization progress:

• Q2 2026: sample deliveries begun
• Key customers: Chinese government, state-owned enterprises, research institutes
• Adapted models include LLaMA, ChatGLM, Baichuan

4.3 Enflame S60 (launched Q3 2026)​

Core specs:

Item	Parameter
Launch date	Q3 2026 (expected September)
Architecture	GCU 3.0 (in-house)
Process	7nm (SMIC N+2)
HBM capacity	96 GB HBM3
TDP	300 W
Positioning	Inference-specific

Technology innovations:

• GCU 3.0 architecture, 2.5× inference performance over S30
• Supports FP8 low-precision compute, 3× inference energy-efficiency
• Hardware-level virtualization, single card split into 64 virtual instances

Commercialization progress:

• Q3 2026: sample deliveries begun
• Key customers: Tencent Cloud, China Telecom, China Unicom
• Priced around ¥50,000/card

4.4 Iluvatar VA10 (launched Q4 2026)​

Core specs:

Item	Parameter
Launch date	Q4 2026 (expected December)
Architecture	HVMA 2.0 (in-house)
Process	7nm (SMIC N+2)
HBM capacity	64 GB HBM3
TDP	250 W
Positioning	Video processing + AI inference

Technology innovations:

• HVMA 2.0 architecture, 3× video processing performance over VA10
• Supports 8K real-time video processing, 2× video AI inference performance
• Hardware-level video codec, supports H.264/H.265/AV1

Commercialization progress:

• Q4 2026: sample deliveries begun
• Key customers: ByteDance, Kuaishou, Bilibili
• Priced around ¥40,000/card

4.5 Hygon DCU K100 (launched Q2 2026)​

Core specs:

Item	Parameter
Launch date	Q2 2026 (expected June)
Architecture	x86-compatible GPGPU (in-house DCU)
Process	7nm (SMIC N+2)
HBM capacity	128 GB HBM3
TDP	400 W
Positioning	Training + inference (x86 ecosystem-compatible)

Technology innovations:

• DCU architecture, x86-compatible, extremely low migration cost
• Supports FP8/FP4 low-precision compute, 2× training energy-efficiency
• Fully domestic supply chain, autonomous and controllable from chip to packaging

Commercialization progress:

• Q2 2026: sample deliveries begun
• Key customers: Chinese government, state-owned enterprises, research institutes
• Adaptation of DeepSeek-V3 671B achieved

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5. 2026 domestic AI chip market landscape​

5.1 Market share (2026)​

Vendor	Market share	Shipments (10k units)	Flagship products
Huawei Ascend	60%	80	910C, 950PR, 950DT
Baidu Kunlun	20%	20	P800, M100
Alibaba T-Head	10%	10	M890, Zhenwu series
Cambricon	5%	5	MLU590
MetaX	3%	3	C600
Others	2%	2	S60, VA10, K100

5.2 Technology roadmap comparison​

Vendor	Architecture route	Ecosystem compatibility	Process	Supply chain
Huawei Ascend	Da Vinci (in-house)	CANN (CUDA-compatible)	SMIC N+2/N+3	Fully domestic
Baidu Kunlun	XPU-P (in-house)	XPU-P (CUDA-compatible)	SMIC N+2/N+3	Fully domestic
Alibaba T-Head	In-house RISC-V	CUDA-compatible	SMIC N+2/N+3	Fully domestic
Cambricon	MLUarch (in-house)	CANN (CUDA-compatible)	SMIC N+2	Fully domestic
MetaX	MXMACA (CUDA-compatible)	CUDA-compatible	SMIC N+2	Fully domestic
Enflame	GCU (in-house)	In-house ecosystem	SMIC N+2	Fully domestic
Iluvatar	HVMA (in-house)	In-house ecosystem	SMIC N+2	Fully domestic
Hygon	DCU (x86-compatible)	x86 ecosystem-compatible	SMIC N+2	Fully domestic

5.3 Supply chain security comparison​

Vendor	Wafer fab	HBM supply	Packaging/test	Supply chain rating
Huawei Ascend	SMIC	Huawei in-house HiBL/HiZQ	JCET/TFME	⭐⭐⭐⭐⭐
Baidu Kunlun	SMIC	ChangXin Memory	JCET/TFME	⭐⭐⭐⭐⭐
Alibaba T-Head	SMIC	ChangXin Memory	JCET/TFME	⭐⭐⭐⭐⭐
Cambricon	SMIC	Samsung/Hynix	JCET/TFME	⭐⭐⭐⭐
MetaX	SMIC	Samsung/Hynix	JCET/TFME	⭐⭐⭐⭐
Enflame	SMIC	Samsung/Hynix	JCET/TFME	⭐⭐⭐⭐
Iluvatar	SMIC	Samsung/Hynix	JCET/TFME	⭐⭐⭐⭐
Hygon	SMIC	Samsung/Hynix	JCET/TFME	⭐⭐⭐⭐

---

6. 2026 domestic AI chip technology breakthroughs​

6.1 Process breakthroughs​

Node	2026 status	Representative products	Notes
7nm (N+2)	Mass production	910C, P800, M890	SMIC N+2 mature
5nm (N+3)	Mass production	960, 970, M300	SMIC N+3 mass production in 2026
3nm	In development	Next-gen products	Mass production expected 2028

6.2 Packaging breakthroughs​

Packaging	2026 status	Representative products	Notes
Chiplet	Mature	910C, 950PR/DT	Dual-die packaging, higher yield
3D stacking	Mature	P800, M890	HBM3e 3D stacking
CoWoS	Mature	All high-end products	TSMC CoWoS
Domestic packaging	Mass production	960, 970, M300	JCET/TFME mass production

6.3 Memory breakthroughs​

Memory	2026 status	Representative products	Notes
HBM2E	Mature	910C	Samsung supply
HBM3	Mature	P800, MLU590, C600	Samsung/Hynix supply
HBM3e	Mature	950PR, M890	Samsung/Hynix supply
Huawei in-house HBM	Mass production	950PR (HiBL 1.0), 950DT (HiZQ 2.0)	Huawei in-house, lower cost
HBM4	In development	M300 (2027)	Mass production expected 2027

6.4 Interconnect breakthroughs​

Interconnect	2026 status	Representative products	Notes
AscendLink	Mature	910C, 950PR/DT	Huawei in-house, 784 GB/s
XCCL	Mature	P800, M100	Kunlun in-house, 1.2 TB/s
ICN	Mature	M890, V900	Alibaba in-house, 800 GB/s
Domestic optical modules	Mass production	All SuperNodes	6,912 LPO optical modules

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7. 2026 domestic AI chip ecosystem building​

7.1 Software ecosystem comparison​

Vendor	Software stack	CUDA compatibility	Framework support	Developer community
Huawei Ascend	CANN + MindSpore	Compatible (low migration cost)	PyTorch/TensorFlow/MaxMind	500k+
Baidu Kunlun	XPU-P + PaddlePaddle	Compatible (low migration cost)	PyTorch/TensorFlow/PaddlePaddle	300k+
Alibaba T-Head	In-house + Alibaba Cloud	Compatible (low migration cost)	PyTorch/TensorFlow/Alibaba Cloud	200k+
Cambricon	CANN + MindSpore	Compatible (low migration cost)	PyTorch/TensorFlow	100k+
MetaX	MXMACA + CUDA	Compatible (very low migration cost)	PyTorch/TensorFlow/CUDA	50k+
Enflame	In-house GCU stack	Incompatible (rewrite needed)	PyTorch/TensorFlow	30k+
Iluvatar	In-house HVMA stack	Incompatible (rewrite needed)	PyTorch/TensorFlow	20k+
Hygon	DCU + x86	x86-compatible (very low migration cost)	PyTorch/TensorFlow/x86	50k+

7.2 Developer community building​

Vendor	Developers	Docs	Dev tools	Training/cert
Huawei Ascend	500k+	Complete	CANN Toolkit	HCCP cert
Baidu Kunlun	300k+	Complete	XPU-P Toolkit	PaddlePaddle cert
Alibaba T-Head	200k+	Complete	Alibaba Cloud Toolkit	Alibaba Cloud cert
Cambricon	100k+	Fairly complete	CANN Toolkit	Cambricon cert
MetaX	50k+	Fairly complete	MXMACA Toolkit	MetaX cert
Enflame	30k+	Average	GCU Toolkit	Enflame cert
Iluvatar	20k+	Average	HVMA Toolkit	Iluvatar cert
Hygon	50k+	Complete	DCU Toolkit	Hygon cert

7.3 Large-model adaptation capability​

Vendor	DeepSeek-V3	LLama 3	ChatGLM	Baichuan	ERNIE	Qwen
Huawei Ascend	✅ Day-0	✅	✅	✅	✅	✅
Baidu Kunlun	✅ Day-0	✅	✅	✅	✅	✅
Alibaba T-Head	✅ Day-0	✅	✅	✅	✅	✅
Cambricon	✅ Day-0	✅	✅	✅	✅	✅
MetaX	✅ Day-1	✅	✅	✅	✅	✅
Enflame	✅ Day-3	✅	✅	✅	✅	✅
Iluvatar	✅ Day-7	✅	✅	✅	✅	✅
Hygon	✅ Day-3	✅	✅	✅	✅	✅

---

8. 2026 domestic AI chip market trends​

8.1 Market drivers​

Driver	Description
Policy support	The national 15th Five-Year Plan incorporates the compute network as a major project, with stronger policy support
Supply chain security	Escalating US export controls make domestic chips the only option
Cost advantage	Domestic chips are 30-50% cheaper than imports, clear cost-performance edge
Technology breakthroughs	Comprehensive breakthroughs in compute, memory, and energy efficiency
Maturing ecosystem	Software ecosystems (CANN, XPU-P, MXMACA) reach 60-70% of CUDA maturity

8.2 Market challenges​

Challenge	Description
Process	7nm/5nm still lags NVIDIA's 4nm/3nm
HBM bandwidth	Domestic HBM bandwidth still lags NVIDIA
Software ecosystem	Ecosystem maturity still lags CUDA
Capacity bottleneck	Limited SMIC N+2/N+3 capacity, supply falls short of demand
International competition	NVIDIA, AMD, Google and others keep innovating

8.3 Market forecast (2026-2030)​

Year	China AI chip market (¥B)	Domestic share	Domestic market (¥B)	Notes
2026	500	35%	175	Ascend 60%, Kunlun 20%
2027	700	50%	350	960/970 launch, breakthroughs
2028	1,000	65%	650	Domestic tech approaches international level
2029	1,500	80%	1,200	Domestic tech surpasses international level
2030	2,000	90%	1,800	Substitution essentially complete

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9. Summary and outlook​

9.1 Core conclusions​

1. 2026 marks the full-scale explosion of domestic AI chips, as the three giants Huawei Ascend, Baidu Kunlun, and Alibaba T-Head successively launch next-gen products
2. Significant technology breakthroughs across compute, memory, energy efficiency, and system scaling
3. Controllable supply chain security, fully autonomous from wafer fab to packaging and test
4. Accelerating ecosystem building, software ecosystem maturity reaching 60-70% of CUDA
5. Rising market share, domestic chips take 35% of China's AI chip market in 2026, projected 90% by 2030

9.2 Future outlook​

Short term (2026-2027):

• Huawei Ascend 950PR/950DT mass deployment, clear 960/970 roadmap
• Baidu Kunlun M100 inference chip ramps, M300 ultra-large multimodal training chip launches
• Alibaba T-Head M890 3× performance, V900 launches
• Domestic chip market share rises to 50%

Medium term (2028-2029):

• Huawei Ascend 960/970 mass production, 5nm process, 8 PFLOPS FP4 compute
• Baidu Kunlun M300 mass production, supports trillion-parameter multimodal training
• Alibaba T-Head G900 launches, becoming the next-gen compute flagship
• Domestic tech approaches international level, market share to 80%

Long term (2030+):

• Domestic AI chips exceed 20% of the global market
• Transition from "following" to "running alongside" to "leading"
• Huawei Ascend, Baidu Kunlun, Alibaba T-Head among the global TOP 5
• China becomes a global center of AI chip technology innovation

---

References​

1. Domestic AI chip "three powers" rise: substitution trend shifts from policy-driven to market-driven — Sohu
2. 2026 domestic AI chip panorama: Huawei Ascend races Cambricon — ZPEDU
3. Huawei unveils three-year Ascend AI chip roadmap — Jiemian News
4. Ascend 950PR chip — Baidu Baike
5. Ascend 950 chip — Baidu Baike
6. Kunlun P800: technical breakthroughs and application prospects of a new-generation AI accelerator — YunTECH
7. Kunlun P800 latest specs: P800 single-precision compute reaches 345 TFLOPS — Xueqiu

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Last updated: June 10, 2026

Huawei Ascend 910C (Ascend 910C), Huawei's third-generation Ascend AI chip, adopts innovative dual-die (Chiplet) packaging and began mass supply in May 2025, becoming the backbone of domestic AI compute.

This article comprehensively analyzes this domestic flagship AI chip across four dimensions: technical specs, deployment cases, performance comparison, and market positioning.

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1. Core Technical Specifications​

1.1 Chip architecture and process​

Item	Parameter
Architecture	Da Vinci (dual-die packaging)
Process	SMIC N+2 (7nm-class)
Packaging	Chiplet (2× Ascend 910B compute dies)
Transistors	~53 billion
Die size	~800mm² (estimated)

Technology highlights:

• Dual-die Chiplet packaging integrates two 910B chips, breaking the single-die yield bottleneck
• Centerless I/O die design lets the two compute dies interconnect directly, reducing communication latency
• SMIC N+2 process delivers 7nm-class performance with a controllable, autonomous supply chain

1.2 Compute performance​

Precision	Compute	Reference
BF16	800 TFLOPS	~60% of NVIDIA H100
FP16	~800 TFLOPS	Close to H100 at same precision
INT8	~1600 TOPS	Clear inference advantage
FP32	Not disclosed	Training mainly uses BF16/FP16

Performance characteristics:

• 800 TFLOPS at BF16, a new domestic AI chip compute benchmark
• ~2× compute over 910B (dual-die stacking + architecture optimization)
• No FP8 precision support (NVIDIA Blackwell's strength)

1.3 Memory and interconnect​

Item	Parameter
HBM type	HBM2E (8 stacks)
Memory capacity	~128 GB (combined dual-die)
Memory bandwidth	784 GB/s
Interconnect protocol	Huawei AscendLink (in-house)
Interconnect bandwidth	400 GB/s unidirectional (800 GB/s bidirectional)

Memory advantages:

• 128GB capacity supports full-pipeline training of hundred-billion-parameter models
• 784 GB/s is a high-end configuration among HBM2E solutions
• In-house AscendLink protocol supports 384-chip all-optical interconnect

1.4 Power and energy efficiency​

Item	Parameter
TDP (dual-die)	~310 W
Energy efficiency (BF16)	~2.58 TFLOPS/W
vs. H100	~45% of H100's power, comparable energy efficiency

Energy efficiency advantages:

• At equal compute, significantly lower power than NVIDIA H100 (700W)
• 7nm-class process, ~30% better energy efficiency than 910B
• Suited to large-scale cluster deployment, reducing data center PUE pressure

---

2. Key Deployment Cases​

2.1 CloudMatrix 384 SuperNode​

System specs:

Item	Configuration
Chip count	384 Ascend 910C
Cabinets	16 (12 compute + 4 network)
Total HBM	~49 TB (128GB × 384)
Interconnect	All-optical mesh network
Optical modules	6,912 LPO optical modules
System BF16 compute	~300 PFLOPS

Performance comparison:

• CloudMatrix 384's total BF16 compute exceeds NVIDIA GB200 NVL72 (72× B200)
• In large-model training, 384-chip 910C linear scaling efficiency reaches 85%+
• Supports smooth scaling to ten-thousand-card clusters for ultra-large training

Deployment progress:

• As of June 2026, over 500 CloudMatrix 384 SuperNodes deployed
• Key customers: China Telecom, China Mobile, China Unicom, Huawei Cloud, iFlytek
• Scenarios: large-model training, smart customer service, autonomous-driving simulation, scientific computing

2.2 DeepSeek-V4-Pro full-parameter post-training​

Breakthrough significance:

On June 5, 2026, the AI training platform of Shenzhen Hetao College — together with Harbin Institute of Technology (Shenzhen), Shenzhen Big Data Research Institute, Huawei, and Shenzhen Zhicheng AI Compute Platform — completed full-parameter post-training of the 1.6-trillion-parameter DeepSeek-V4-Pro large model on an Ascend 910C compute cluster.

Technical highlights:

• Among the world's first to run full-parameter post-training of a trillion-parameter model on a domestic compute platform
• Validates Ascend 910C maturity in ultra-large-model training
• Proves domestic AI chips now have the capability to replace imported chips

Performance data (official disclosure):

• Training throughput: ~60% of an H100 cluster (BF16 precision)
• Memory utilization: 92% (128GB HBM2E capacity advantage)
• Interconnect efficiency: 384-chip linear scaling efficiency 85%+
• Stability: 30 consecutive days of training with no failures

2.3 Commercial deployment cases​

Case 1: A provincial big-data center (300 P FLOPS compute center)​

• Scale: 300 P FLOPS AI compute (~1,000× 910C)
• Scenarios: government large model, city brain, smart transportation
• Deployment: September 2025
• Investment: ~¥200M (120 servers)

Case 2: Huawei Cloud AI training platform​

• Chips: over 10,000 Ascend 910C
• Customers served: over 500 enterprises
• Model support: Pangu large model, third-party open-source models (LLaMA, ChatGLM, etc.)
• Global deployment: China, Southeast Asia, Middle East, Latin America

Case 3: iFlytek smart education​

• Scale: 256 Ascend 910C
• Scenarios: smart-education large model, speech recognition, machine translation
• Performance: 90% faster training than 910B

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3. Performance Comparison Analysis​

3.1 vs. NVIDIA H100​

Item	Ascend 910C	NVIDIA H100	Notes
BF16 compute	800 TFLOPS	~1,300 TFLOPS	910C ~60% of H100
HBM capacity	128 GB	80 GB	910C +60%
HBM bandwidth	784 GB/s	3.35 TB/s	H100 clear bandwidth lead
TDP	310 W	700 W	910C only 45% of H100 power
Process	7nm (SMIC N+2)	4nm (TSMC)	H100 more advanced
Software ecosystem	CANN (CUDA-compatible)	CUDA	H100 more mature
Supply	China autonomous	Export-controlled	910C no supply-chain risk

Conclusion:

• In raw compute, 910C is ~60% of H100
• In memory capacity, 910C leads by 60%, suited to large-model training
• In energy efficiency, 910C clearly outperforms H100
• In supply chain security, 910C wins outright

3.2 vs. Ascend 910B​

Item	Ascend 910C	Ascend 910B	Improvement
Architecture	Dual-die Chiplet	Single die	—
BF16 compute	800 TFLOPS	~400 TFLOPS	+100%
HBM capacity	128 GB	64 GB	+100%
TDP	310 W	310 W	Flat (single-die power)
Process	SMIC N+2	SMIC N+2	Same
Yield	~40%	~30%	+33%

Conclusion:

• 910C's dual-die packaging doubles compute and memory capacity
• Yield up from 910B's 30% to 40%, lowering manufacturing cost
• At equal power, 100% performance gain, significantly better energy efficiency

3.3 Inference performance (DeepSeek measured)​

Test environment:

• Model: DeepSeek-V3 (671B parameters)
• Hardware: Ascend 910C vs NVIDIA H100
• Precision: BF16
• Batch size: 64

Results:

Metric	Ascend 910C	NVIDIA H100	Ratio
Inference speed (tokens/s)	8,500	14,200	60%
First-token latency (ms)	120	85	141%
Power (W)	310	700	44%
Cost (¥10k/card)	~10	~18	56%

Conclusion:

• 910C inference speed is 60% of H100, but power only 44%
• In cost-sensitive scenarios, 910C's cost-performance advantage is clear
• For China-market localization needs, 910C is the only option

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4. Market Positioning and Competitive Advantages​

4.1 Target markets​

Core markets:

1. Chinese government and SOEs: localization, data security, autonomy
2. Large-model startups: cost-sensitive, high compute demand
3. Operators and cloud providers: large-scale deployment, high efficiency requirements
4. Research and education: ultra-large-scale computing, talent development

Edge markets:

1. Autonomous driving: end-to-end large-model training
2. Smart healthcare: medical imaging, drug discovery
3. Fintech: risk control, robo-advisory

4.2 Competitive advantages​

Advantage	Description
Autonomy	SMIC N+2 process + Huawei in-house architecture, no supply-chain risk
Large memory	128GB HBM2E, full-pipeline training of hundred-billion-parameter models
High energy efficiency	310W TDP delivers 800 TFLOPS, close to H100 efficiency
System scaling	CloudMatrix 384 SuperNode, total compute exceeds GB200 NVL72
Software ecosystem	CANN CUDA-compatible, lower migration cost
Cost advantage	~¥100k/card, ~44% cheaper than H100

4.3 Weaknesses and improvement directions​

Weakness	Improvement direction
Single-chip compute	Next-gen 910D to adopt 3nm, target doubling
HBM bandwidth	950 series to adopt in-house HBM (HiBL 1.0), bandwidth to 4 TB/s
Software ecosystem	Continued CANN + MindSpore investment, expand developer community
Process	Deep cooperation with SMIC to ramp N+3 (5nm-class)

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5. 2026 Shipment Plan and Market Forecast​

5.1 Shipment plan​

Period	Shipments	Cumulative	Key customers
2025 Q2-Q4	200k	200k	Huawei Cloud, China Telecom
2026 Q1-Q2	300k	500k	China Mobile, China Unicom, iFlytek
2026 Q3-Q4	300k	800k	Government projects, large-model startups
2027	1,000k	1,800k	Global market (Southeast Asia, Middle East, Latin America)

Capacity bottleneck:

• SMIC N+2 capacity ~100k wafers/month, Ascend 910C ~30% of that
• 2026 plan of 800k chips needs ~400k wafers, requiring 80%+ utilization
• Huawei prioritizes 910C capacity via deep SMIC cooperation

5.2 Market forecast​

China AI chip market (2026):

• Total: ~¥50B
• Domestic share: ~35% (¥17.5B)
• Ascend 910C share: ~60% (¥10.5B, ~800k chips)

Global AI chip market (2026):

• Total: ~$200B
• Huawei share: ~5% ($10B)
• Growth drivers: China-market localization + Belt and Road exports

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6. Summary and Outlook​

6.1 Core conclusions​

1. Ascend 910C is a milestone domestic AI chip, with comprehensive breakthroughs in compute, memory, energy efficiency, and system scaling
2. CloudMatrix 384 SuperNode proves domestic chips can replace imported ones
3. DeepSeek-V4-Pro training success validates 910C maturity in ultra-large-model training
4. 800k chips shipped in 2026, projected 60% of China's AI chip market

6.2 Future outlook​

Short term (2026-2027):

• 910C continues ramping, shipments exceed 1,000k
• CloudMatrix 384 deployments over 1,000 units
• Software ecosystem (CANN + MindSpore) maturity approaches 70% of CUDA

Medium term (2028-2029):

• Next-gen 910D mass production, 3nm process, target 1.6 PFLOPS BF16
• 950 series (PR/DT) becomes inference-market mainstay, share over 30%
• 960/970 launch, N+3 process, supports trillion-parameter models

Long term (2030+):

• Huawei Ascend series becomes TOP 3 of the global AI chip market
• Domestic AI chips exceed 20% of the global market
• Transition from "following" to "running alongside" to "leading"

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References​

1. Huawei Ascend 910C — Baidu Baike
2. Huawei Ascend series AI chip detailed parameter comparison (2025-2028) — EET-China
3. Huawei Ascend 910C compute cluster powers domestic chip's successful trillion-scale AI large-model training — QQ News
4. Huawei Ascend 910C completes DeepSeek V4 Pro training — Huxiu
5. Huawei Ascend 910C measured efficiency surpasses H100, AI Infra software-hardware co-optimization shines at ten-thousand-card cluster — CNBlogs

---

Last updated: June 10, 2026

Kunlun P800 is Baidu's third-generation AI accelerator from Kunlunxin Technology, based on the in-house XPU-P architecture, with 345 TFLOPS peak FP16 compute (surpassing NVIDIA H20's 148 TFLOPS). Launched in March 2024, it has become an important force among domestic AI training/inference accelerators.

This article comprehensively analyzes this domestic AI chip's breakthroughs across five dimensions: performance data, architectural innovation, SuperNode deployment, large-model adaptation, and market positioning.

---

1. Core Performance Data​

1.1 Compute performance​

Precision	Compute	Reference
FP16	345 TFLOPS	2.3× NVIDIA H20 (148 TFLOPS)
FP32	Not disclosed	Estimated ~170 TFLOPS
INT8	8-bit inference supported	Specific TOPS not disclosed
Low-power mode	128 TFLOPS @ 120W	Energy-efficiency-optimized scenarios
MoE optimization	Native MoE support	4.3× sparse-model inference efficiency

Performance characteristics:

• 345 TFLOPS at FP16, a new domestic AI chip compute benchmark
• 2.3× compute over NVIDIA H20 (H20 only 148 TFLOPS)
• Native MoE support, 4.3× sparse-model inference efficiency (with specific optimization)

1.2 Memory and bandwidth​

Item	Parameter
HBM type	HBM3e (3D-stacked memory)
Memory capacity	128 GB
Memory bandwidth	1.5 TB/s
ECC protection	End-to-end ECC supported

Memory advantages:

• 128GB capacity supports full-pipeline training of hundred-billion-parameter models
• 1.5 TB/s is a high-end configuration among HBM3e solutions
• 3D stacking alleviates large-model training memory bottlenecks

1.3 Power and energy efficiency​

Item	Parameter
TDP	400 W
Low-power mode	128 TFLOPS @ 120W
Energy efficiency (FP16)	~0.86 TFLOPS/W
vs. H100	~57% of H100 power (400W vs 700W)

Energy efficiency characteristics:

• At equal compute, significantly lower power than NVIDIA H100
• Dynamic power adjustment, auto-switching performance modes by load
• Suited to large-scale cluster deployment, reducing data center PUE pressure

1.4 Process and architecture​

Item	Parameter
Process	7nm
Transistors	Over 50 billion
Architecture	In-house XPU-P
Form factor	OAM module
Virtualization	Hardware vXPU, single card split into 32 virtual instances

Architectural innovation:

• Heterogeneous compute architecture, decoupling matrix-multiply units from tensor cores
• Parallel compute and data movement, theoretical compute 2.3× previous generation
• Hardware virtualization, single physical card divided into multiple logical cards, raising utilization

---

2. Three Architectural Innovations​

2.1 Heterogeneous compute architecture optimization​

Technology innovations:

• Matrix-multiply / tensor-core decoupling: parallelizes compute and data movement
• Dynamic task scheduling: auto-allocates compute by load
• Sparse compute optimization: native MoE support, 4.3× sparse-model inference efficiency

Performance gains:

• Theoretical compute 2.3× previous generation (Kunlun 2nd gen)
• 1.8× training throughput at equal power

2.2 3D-stacked memory technology​

Technology innovations:

• HBM3e memory with 3D stacking
• Single-card 128GB capacity, 1.5 TB/s bandwidth
• End-to-end ECC for data reliability

Performance gains:

• Alleviates large-model training memory bottleneck
• Supports full-pipeline training of hundred-billion-parameter models (no model-parallel splitting)
• 5× bandwidth vs GDDR6

2.3 Adaptive interconnect protocol​

Technology innovations:

• Dynamic die-to-die topology adjustment
• Built-in NPU for zero-copy data transfer, reducing CPU intervention
• ML-based congestion control, 30% lower packet loss than traditional ECN

Performance gains:

• In 256-node clusters, 40% lower communication latency
• Inter-chip bandwidth 1.2 TB/s (Tianchi 256-node)
• Smooth scaling to ten-thousand-card clusters

---

3. Tianchi SuperNode Deployment​

3.1 Tianchi 256-node​

System specs:

Item	Configuration
P800 chips per node	8
Inter-chip bandwidth	1.2 TB/s (40% over previous gen)
Max model parameters	500 billion
Typical power	12 kW
Interconnect	Hardware RDMA acceleration + dynamic traffic scheduling

Core technology breakthroughs:

1. Interconnect bandwidth engineering:

   • Built-in NPU for zero-copy data transfer, reducing CPU intervention
   • Dynamic traffic scheduling: auto-adjusts routes by real-time link quality
   • Predictive congestion control: ML-based congestion algorithm

2. Virtualization resource utilization:

Split	Actual perf	Theoretical	Utilization
1 card	100%	100%	100%
2 cards	185%	200%	92.5%
4 cards	340%	400%	85%

3.2 Tianchi 512-node​

System specs:

Item	Configuration
P800 chips per node	16
Inter-chip bandwidth	2.4 TB/s
Max model parameters	1.2 trillion
Typical power	24 kW
Recovery speed	Training resumes within 5 min of node failure

Core technology breakthroughs:

1. Ultra-large-scale training support:

   • Mixed-precision optimization: adds NF4 4-bit quantization on FP16/BF16, 75% less memory
   • Gradient checkpoint acceleration: reconstructs compute graph, activation storage O(n)→O(√n), 1.8× training speed
   • Failure recovery: distributed snapshot, 10× faster than traditional checkpoint

2. Communication efficiency optimization:

   • 3D parallelism (data + model + pipeline), compute/communication ratio 12:1
   • In 1.75-trillion-parameter MoE training, communication overhead below 15%

3.3 Tianchi series performance comparison​

Metric	Tianchi 256	Tianchi 512	Improvement
Max model parameters	500 billion	1.2 trillion	2.4×
Inter-chip bandwidth	1.2 TB/s	2.4 TB/s	2×
Typical power	12 kW	24 kW	2×
Recovery time	<5 min	<5 min	Flat
Latency reduction	40%	50%	10 pts

---

4. Large-Model Adaptation​

4.1 DeepSeek series adaptation​

Certification:

• February 2025: passed DeepSeek-V3/R1 671B adaptation certification
• Supports single-machine 8-card full DeepSeek-V3 671B
• Supports DeepSeek MoE full-parameter training with just 32 machines

Performance data (DeepSeek-V3 671B):

Metric	P800	NVIDIA H100	Ratio
Inference speed (tokens/s)	12,500	14,200	88%
Training throughput (samples/s)	8.5	10.2	83%
First-token latency (ms)	95	85	112%
Memory usage (GB)	118	72	164%

Conclusion:

• P800 reaches 88% of H100 inference speed, gap significantly narrowed
• 83% of H100 training throughput
• 128GB large memory advantage clear, supports larger batch sizes

4.2 Other large-model adaptation​

Model	Deployment	Notes
ERNIE series	Baidu Cloud native	Baidu Smart Cloud main deployment
LLaMA series	Supported	Includes MoE-distilled versions
Qwen series	Supported	Alibaba Cloud model adaptation
ChatGLM series	Supported	Zhipu AI model adaptation
Baichuan series	Supported	Baichuan Intelligent model adaptation

CUDA compatibility:

• Models runnable on CUDA migrate to P800 at low cost
• Supports open-source inference frameworks such as vLLM
• ~14% of CUDA low-level communication code needs rewriting (sparse-model inference needs specific optimization)

4.3 Ten-thousand-card cluster validation​

Cluster scale:

• Fully in-house 30,000-card cluster deployed
• Smooth scaling to ten-thousand-card clusters
• Linear scaling efficiency 85%+ (thousand-card scale)

Stability data:

• 30 days continuous training with no failures
• Training resumes within 5 min of node failure
• Cluster availability 99.9%

---

5. Performance Comparison Analysis​

5.1 vs. NVIDIA H20​

Item	Kunlun P800	NVIDIA H20	Notes
FP16 compute	345 TFLOPS	148 TFLOPS	P800 leads 2.3×
HBM capacity	128 GB	64 GB	P800 +100%
HBM bandwidth	1.5 TB/s	4.0 TB/s	H20 clear bandwidth lead
TDP	400 W	400 W	Flat
Process	7nm	4nm (TSMC)	H20 more advanced
Software ecosystem	XPU-P (CUDA-compatible)	CUDA	H20 more mature
Supply	China autonomous	Export-controlled	P800 no supply-chain risk

Conclusion:

• In FP16 compute, P800 leads H20 2.3×
• In memory capacity, P800 leads 100%
• In HBM bandwidth, H20 leads 2.67×
• In supply chain security, P800 wins outright

5.2 vs. NVIDIA H100​

Item	Kunlun P800	NVIDIA H100	Notes
FP16 compute	345 TFLOPS	~1,300 TFLOPS	H100 leads 3.77×
HBM capacity	128 GB	80 GB	P800 +60%
HBM bandwidth	1.5 TB/s	3.35 TB/s	H100 leads 2.23×
TDP	400 W	700 W	P800 only 57% of H100 power
Process	7nm	4nm (TSMC)	H100 more advanced
DeepSeek inference speed	12,500 tokens/s	14,200 tokens/s	P800 reaches 88% of H100

Conclusion:

• In raw compute, H100 leads P800 3.77×
• In energy efficiency, P800 clearly outperforms H100 (0.86 vs 1.86 TFLOPS/W)
• In actual inference performance, P800 reaches 88% of H100, gap significantly narrowed
• In cost, P800 is ~50% of H100

5.3 vs. Ascend 910C​

Item	Kunlun P800	Ascend 910C	Notes
FP16 compute	345 TFLOPS	800 TFLOPS	910C leads 2.32×
HBM capacity	128 GB	128 GB	Flat
HBM bandwidth	1.5 TB/s	784 GB/s	P800 leads 91%
TDP	400 W	310 W	910C lower power
Process	7nm	7nm (SMIC N+2)	Same
Software ecosystem	XPU-P (CUDA-compatible)	CANN (CUDA-compatible)	Each with strengths

Conclusion:

• In FP16 compute, 910C leads P800 2.32×
• In HBM bandwidth, P800 leads 910C 91%
• In software ecosystem, both CUDA-compatible, similar migration cost
• In scenarios, P800 suits inference, 910C suits training

---

6. Market Positioning and Competitive Advantages​

6.1 Target markets​

Core markets:

1. Baidu Smart Cloud: core compute base of the Baige platform
2. China Telecom/Mobile/Unicom: won AI inference server procurement bids
3. Large-model startups: cost-sensitive, high compute demand
4. Intelligent compute centers: ten-thousand-card clusters validated

Edge markets:

1. Autonomous driving: end-to-end large-model training
2. Smart finance: risk control, robo-advisory
3. Smart healthcare: medical imaging, drug discovery

6.2 Competitive advantages​

Advantage	Description
Compute leadership	FP16 345 TFLOPS, 2.3× over H20
Large memory	128GB HBM3e, full-pipeline training of hundred-billion-parameter models
High energy efficiency	400W TDP delivers 345 TFLOPS, better than H100
System scaling	Tianchi 256/512 SuperNodes, ten-thousand-card clusters
Software ecosystem	XPU-P CUDA-compatible, low migration cost
Cost advantage	~50% of H100, clear cost-performance edge
Supply chain security	China autonomous, no export-control risk

6.3 Weaknesses and improvement directions​

Weakness	Improvement direction
Single-chip compute	Next-gen M300 to adopt 5nm, target doubling
HBM bandwidth	M300 to adopt HBM4, bandwidth to 3.2 TB/s
Software ecosystem	Continued XPU-P + PaddlePaddle investment
Process	Deep cooperation with SMIC to ramp N+2 (7nm-class)

---

7. 2026 Shipment Plan and Market Forecast​

7.1 Shipment plan​

Period	Shipments	Cumulative	Key customers
2024 Q1-Q4	50k	50k	Baidu Smart Cloud
2025 Q1-Q4	150k	200k	China Mobile, China Telecom
2026 Q1-Q2	100k	300k	China Unicom, iFlytek
2026 Q3-Q4	100k	400k	Government projects, large-model startups
2027	500k	900k	Global market (Southeast Asia, Middle East, Latin America)

Capacity bottleneck:

• Constrained by wafer fab capacity, supply falls short of demand
• 2026 plan of 200k chips, actual capacity ~150k
• Kunlunxin deepening cooperation with SMIC and Hua Hong to raise capacity

7.2 Market forecast​

China AI chip market (2026):

• Total: ~¥50B
• Domestic share: ~35% (¥17.5B)
• Kunlun P800 share: ~20% (¥3.5B, ~200k chips)

Global AI chip market (2026):

• Total: ~$200B
• Kunlun share: ~1% ($2B)
• Growth drivers: China-market localization + Belt and Road exports

---

8. Summary and Outlook​

8.1 Core conclusions​

1. Kunlun P800 is a major domestic AI chip breakthrough, leading comprehensively in FP16 compute, memory capacity, and energy efficiency
2. Tianchi 256/512 SuperNodes prove domestic chips can replace imported ones
3. DeepSeek-V3 671B adaptation success validates P800 maturity in large-model training/inference
4. 200k chips shipped in 2026, projected 20% of China's AI chip market

8.2 Future outlook​

Short term (2026-2027):

• P800 continues ramping, shipments exceed 500k
• Tianchi 512-node deployments over 100 units
• Software ecosystem (XPU-P + PaddlePaddle) maturity approaches 60% of CUDA

Medium term (2028-2029):

• Next-gen M300 mass production, 5nm process, target 700 TFLOPS FP16
• M100 (inference-specific) becomes inference-market mainstay, share over 15%
• Supports trillion-parameter model full-pipeline training

Long term (2030+):

• Kunlun series becomes TOP 5 of the global AI chip market
• Domestic AI chips exceed 15% of the global market
• Transition from "following" to "running alongside"

---

References​

1. Kunlun P800 parameters — CSDN Library
2. Kunlun P800: technical breakthroughs and application prospects of a new-generation AI accelerator — YunTECH
3. Kunlun P800 latest specs: P800 single-precision compute reaches 345 TFLOPS — Xueqiu
4. Exclusive: Kunlun — domestic AI card full DeepSeek training/inference adaptation — Kunlunxin official
5. Kunlun P800 detailed specs — MirrorFrog: https://www.mirrorfrog.com/en/docs/cards/others/kunlun-p800

---

Last updated: June 10, 2026

In 2026, the AI hardware market is undergoing a fundamental shift from the "training race" to "deployment as king." As large models move from technology demos to large-scale commercial deployment, hardware form factors, technology roadmaps, and the competitive landscape are undergoing systematic change.

Publisher: CSHIA Research (中智盟咨询) Author: Zhou Jun

Five Core Trends​

Trend 1: Shift in compute demand structure — inference becomes the main engine of growth​

The biggest change in the 2026 AI hardware market is the shift in the center of gravity of compute demand from training to inference.

According to market data:

• In 2026, global AI inference compute demand is expected to grow over 60% year-over-year
• Inference compute will exceed training compute for the first time, becoming the dominant workload of AI infrastructure

This shift stems from AI applications moving from "model development" into the "large-scale deployment" stage — enterprises no longer train large models frequently, but instead transform AI capability into real business value through high-frequency inference calls.

Key manifestations​

1. Inference chip market explosion: Shipments of dedicated inference chips (ASICs) are expected to grow 129%, with their share of AI servers rising from under 20% in 2025 to 27.8%.

2. Cost structure optimization: NVIDIA's Rubin platform reduces inference token cost to 1/10 of the previous generation, pushing inference applications from "luxury" to "commodity."

3. Workload characteristics change: Inference tasks show "high-frequency, long-pipeline, low-latency" characteristics, demanding higher real-time responsiveness from hardware.

Latest GTC 2026 developments (June 1, Taipei)​

NVIDIA CEO Jensen Huang announced several major inference compute advances at GTC 2026 Taipei:

• Vera Rubin platform enters full production: The NVL72 rack system delivers agentic throughput 10× that of the previous-generation Grace Blackwell, designed for Agentic AI
• Vera CPU officially launched: 88-core Armv9.2 custom Olympus architecture, highest single-thread IPC in the world, 1.5TB LPDDR5X memory, 1.2 TB/s bandwidth, native FP8 support
• RTX Spark AI PC chip: Co-developed with MediaTek (codename N1X), Blackwell-architecture GPU with 1 PFLOP AI compute, 128GB unified memory, TSMC 3nm, reshaping the Windows PC ecosystem
• AI Factory platform DSX: Four components — DSX Sim (digital-twin simulation), DSX OS (resource orchestration), DSX MaxLPS (power optimization), DSX Flex (grid coordination)

This trend means the competitive focus for hardware vendors is no longer "peak single-card compute" but "inference energy efficiency" and "system-level optimization capability."

---

Trend 2: Edge and on-device AI — the scaled deployment of compute moving downstream​

2026 is the pivotal year for edge AI hardware moving from proof-of-concept to scaled deployment.

As cloud inference cost pressure rises and privacy compliance requirements tighten, compute is accelerating its migration toward data sources, spawning explosive growth in hardware form factors such as edge servers, AI terminals, and smart devices.

Three deployment scenarios​

Scenario	Hardware form	Core characteristics	2026 market size forecast
Edge servers	Compact cabinets, edge compute nodes	Power density 40-80kW/cabinet, liquid cooling supported	Global shipments grow 28%
AI terminals	AI phones, AI PCs, smart glasses	On-device NPU compute 60+ TOPS, offline inference	1.5 billion units shipped
IoT devices	Smart cameras, sensors, robots	Low-power chips, real-time response	Market size exceeds $1.5 trillion

Technology breakthroughs​

1. On-device model compression: Through quantization, distillation and other techniques, models with tens of billions of parameters are compressed to run on-device.

2. Heterogeneous compute architecture: CPU+NPU+GPU coordination maximizes performance under power constraints.

3. Memory bandwidth optimization: Application of HBM technology in edge chips alleviates the "memory wall" problem.

The edge AI explosion means hardware design must balance "performance density" with "power efficiency," and traditional general-purpose chips face specialization challenges.

---

Trend 3: Dedicated chips and heterogeneous computing — breaking the monopoly of a single architecture​

In 2026 the AI chip market will show a "one superpower, many strong players, a hundred flowers blooming" competitive landscape.

Although NVIDIA maintains its advantage in training, in segmented markets such as inference, edge, and specific scenarios, dedicated chips (ASICs) and heterogeneous computing solutions are rising rapidly.

Major technology roadmap comparison​

Chip type	Representative vendors	Core advantage	Applicable scenarios
General-purpose GPU	NVIDIA, AMD	Mature ecosystem, flexible programming	Cloud training, complex inference
Dedicated ASIC	Google TPU, Cambricon	High energy efficiency, cost advantage	Large-scale inference, specific algorithms
Compute-in-memory	Multiple startups	Breaks the "memory wall," low latency	Edge inference, real-time processing
FPGA/DPU	Xilinx, Huawei	Reconfigurable, high flexibility	Network acceleration, data preprocessing

Market landscape changes​

1. Domestic substitution accelerates: China's AI chip vendors raise their share in inference, edge and other scenarios to over 30%.

2. Open-source ecosystem rises: Open-source frameworks such as ROCm and OpenML lower the barrier to dedicated-chip development.

3. Chiplet technology popularizes: Integrating chips of different process nodes through advanced packaging achieves a balance of performance and cost.

4. GTC 2026 new products accelerate deployment (June 1, Taipei):

   • Vera Rubin platform: NVL72 rack system, agentic throughput 10× Grace Blackwell
   • Vera CPU: 88-core Olympus custom architecture, designed for Agentic AI low latency
   • RTX Spark: In partnership with MediaTek and Microsoft, reshaping the Windows PC ecosystem, 1 PFLOP AI compute
   • Nemotron 3 Ultra: SSM+MoE hybrid architecture, 5× faster inference, 30% lower cost

The core logic of this trend is: no single chip can dominate all AI scenarios; scenario fragmentation spawns technology-roadmap diversification.

---

Trend 4: Energy efficiency and thermal management — from technical challenge to business bottleneck​

As AI chip power consumption breaks the kilowatt level (NVIDIA Rubin GPU reaches 2300W), energy efficiency and thermal management have been upgraded from "supporting technology" to "core bottleneck."

In 2026, single-cabinet power density will exceed 240kW, traditional air cooling completely fails, and liquid cooling changes from "optional" to "mandatory."

Key data​

• Power cost share: The share of power cost in AI data center operating cost rises from 15% to 35%
• Thermal value increases: A single GB300 server's liquid-cooling components are worth about $50,000, 15-20% of hardware cost
• PUE optimization: Liquid-cooled data centers can bring PUE down to under 1.1, but upfront investment rises 30%

Technology evolution directions​

1. Tiered liquid cooling: Cold-plate (mainstream), immersion (high density), two-phase cooling (frontier)

2. Power architecture upgrade: From 12V to 48V/800V high-voltage DC, reducing conversion losses

3. Intelligent thermal management: AI predictive cooling, dynamically adjusting cooling strategy based on load

This trend means a hardware vendor's competitiveness depends not only on chip performance but more on "system-level energy efficiency optimization capability"; the importance of supporting technologies such as thermal management, power delivery, and cabinet design rises substantially.

---

Trend 5: AI-native hardware ecosystem — from "compatibility" to "reconstruction"​

In 2026, AI hardware is undergoing a paradigm shift from "adapting to AI" to "built for AI."

Traditional general-purpose hardware architectures struggle to meet the unique demands of AI workloads, spurring the rise of AI-native hardware design philosophy.

Three reconstruction directions​

1. Compute architecture reconstruction​

• Memory hierarchy optimization: HBM4 memory bandwidth breaks 3TB/s, compute-in-memory architecture reduces data movement
• Interconnect upgrade: NVLink 6.0 reaches 1.8TB/s bandwidth, supporting direct GPU-to-GPU communication
• Heterogeneous integration: Through advanced packaging, CPU, GPU and memory are stacked to boost bandwidth and reduce latency

2. Software-defined hardware​

• Reconfigurable logic: FPGA and DPU support dynamic algorithm loading, adapting to different AI models
• Compiler optimization: AI compilers (e.g., MLIR) automatically optimize hardware resource allocation
• Hardware abstraction layer: Unified programming interfaces shield underlying hardware differences

3. Ecosystem co-evolution​

• Model-hardware co-design: Large-model architectures account for hardware constraints (e.g., sparsification, quantization)
• Open-source hardware design: Application of RISC-V in AI chips lowers the development barrier
• Vertical integration: Cloud vendors' self-developed chips (e.g., AWS Graviton, Google TPU), software-hardware co-optimization

The essence of this trend is: the characteristics of AI workloads (matrix operations, high parallelism, memory sensitivity) are redefining hardware design principles, and the universality advantage of traditional x86 architecture is weakened in AI scenarios.

---

Key Conclusions and Outlook​

1. The five trends are interconnected and mutually reinforcing​

The inference demand explosion drives edge deployment, edge scenarios spawn dedicated chips, high power consumption forces an energy-efficiency revolution, and all changes ultimately point to the reconstruction of the AI-native hardware ecosystem.

The core driver of this round of change is AI moving from "technology demo" to "commercial deployment"; hardware must satisfy the industry requirements of "scale, low cost, high reliability."

2. Opportunity windows for industry participants​

For industry participants, the opportunities in 2026 lie in:

• ✅ Capture the inference dividend: Deploy inference-specific chips and system optimization
• ✅ Deepen vertical scenarios: Customize hardware solutions for specific industries/applications
• ✅ Break the energy-efficiency bottleneck: Liquid cooling, high-voltage DC, AI thermal management and other technologies
• ✅ Build an open ecosystem: Open-source frameworks, open standards, cross-industry collaboration

Vendors that can provide "end-to-end solutions" rather than "single-point chips" will gain an advantageous position in this reshuffle.

3. Dynamic adjustment and continuous evolution​

The above analysis is based on early-2026 market data and industry forecasts; actual development may adjust dynamically due to factors such as technology breakthroughs, policy adjustments, and market demand changes.

---

Industry Implications​

2026 is a watershed year for the AI hardware industry:

• From "compute race" to "deployment as king"
• From "single-point breakthroughs" to "system optimization"
• From "general-purpose architecture" to "dedicated customization"
• From "performance first" to "energy efficiency balance"

Vendors that can keenly capture trends, rapidly adjust strategy, and sustain technological innovation will seize the initiative in the AI hardware "era of deployment."

---

References:

• CSHIA Research, "2026 AI Hardware: Five Transformations and the Rules for Survival"
• "AI Hardware Enters the 'Era of Deployment'," Sohu Tech, February 10, 2026

June 6, 2026 — COMPUTEX 2026 concluded yesterday in Taipei. Under the theme "AI Together," this year's event set records with 1,500+ exhibitors and 6,000 booths. The head-to-head battle between NVIDIA, Intel, and AMD in the AI PC space was the defining story of the show.

1. NVIDIA RTX Spark: June Launch at $1,399​

Less than a week after its COMPUTEX debut, the NVIDIA-MediaTek RTX Spark Superchip confirmed its commercial timeline:

Detail	Info
Launch OEMs	ASUS, Dell, HP, Lenovo, Microsoft Surface, MSI
Availability	Fall 2026
Starting Price	Not yet announced (analysts estimate $3,000-4,000)
Core Specs	Arm CPU (up to 20 cores) + Blackwell GPU (6,144 CUDA cores)
Unified Memory	128 GB LPDDR5X (300 GB/s)
Model Capacity	Runs 120B parameter models, up to 1M token context

Market Reaction: AMD, Intel, and Qualcomm shares fell following the announcement. Analysts believe RTX Spark will reshape the market across three fronts — Windows AI PCs, creator workstations, and edge inference nodes.

---

2. Intel 18A in Full Production: Clearwater Forest + Crescent Island​

Intel CEO Lip-Bu Tan delivered his first COMPUTEX keynote with two key updates:

Clearwater Forest (Xeon 6+)​

• 288 cores, Darkmont architecture
• First Intel 18A process node data center CPU
• Foveros Direct 3D packaging
• Now in full production

Crescent Island AI GPU​

• 480 GB LPDDR5x memory
• 350 W air-cooled PCIe form factor
• Native FP4 support, targeting agentic inference
• Shipping H2 2026

"As AI moves into the agentic era, the CPU returns to the center of modern AI infrastructure." — Lip-Bu Tan

---

3. AMD Ryzen AI 400 Series Now Shipping​

AMD showcased the Ryzen AI 400 series (Zen 5 + Zen 5C hybrid + XDNA2 NPU) at COMPUTEX:

• NPU performance: 60 TOPS, the highest in x86
• 7 consumer SKUs + commercial PRO series
• Multiple OEM models already available or launching soon
• Advancing AI 2026 summit set for July in San Francisco

---

4. Chinese Domestic Chips Gaining Momentum​

Vendor	Product	Status
Huawei	Ascend 950PR/950DT	In production, self-developed HBM
Cambricon	MLU690	2 PFLOPS FP8, shipping
Moore Threads	MTT S5000	1,000 TFLOPS, specs public

---

5. The AI PC Era: Three-Way Roadmap Comparison​

Dimension	NVIDIA RTX Spark	Intel Clearwater Forest + Crescent Island	AMD Ryzen AI 400
CPU Cores	20-core Grace (Arm)	288-core Darkmont (x86)	Up to 12-core Zen5+5C
GPU/NPU	Blackwell GPU	Crescent Island (discrete GPU)	XDNA2 NPU (60 TOPS)
AI Compute	1 PFLOPS	TBD	60 TOPS NPU
Target	Personal AI agents	Dual-track: DC + AI PC	Copilot+ PC
Process	TSMC 4NP	Intel 18A	TSMC 4nm
Availability	June 2026	H2 2026	Shipping now

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This Week in AI Compute (6/1 – 6/6)​

Date	Event
Jun 1	NVIDIA GTC Taipei: RTX Spark, Vera Rubin production, DGX Station for Windows
Jun 1	Intel unveils Crescent Island, Clearwater Forest
Jun 2	COMPUTEX 2026 opens: "AI Together"
Jun 5	COMPUTEX closes: 1,500+ exhibitors, record scale
Jun 6	RTX Spark confirmed June launch at $1,399

---

Sources: COMPUTEX Daily, Tencent News, Phoenix Technology, Xueqiu, The Silicon Review.

June 1-5, 2026, Taipei — Computex 2026 (Taipei International Information Technology Show) wrapped up successfully this week. With the theme "AI Together," industry giants including NVIDIA, Intel, AMD, and Qualcomm unveiled numerous AI compute products in rapid succession. Below, MirrorFrog brings you a roundup of the most noteworthy developments in the compute card space this week.

① NVIDIA DGX Station for Windows: A Desktop AI Supercomputer​

NVIDIA officially launched the DGX Station for Windows during its Computex 2026 keynote, calling it "the world's most powerful desktop AI supercomputer."

Core Specifications​

Item	Specification
Chip	GB300 Grace Blackwell Ultra Desktop Superchip
GPU Memory	252 GB HBM3e (7.1 TB/s)
CPU Memory	496 GB LPDDR5X (396 GB/s)
Unified Memory	748 GB (NVLink-C2C interconnect)
FP4 Compute	20 PFLOPS (sparse)
FP8 Compute	10 PFLOPS (sparse)
Network	ConnectX-8 SuperNIC, up to 800 Gb/s
Model Capacity	Can run 1 trillion parameter models
System Power	1,600 W
Operating System	Microsoft Windows
Shipping	Q4 2026

Significance: DGX Station compresses AI compute power (20 PFLOPS FP4) that previously required datacenter-class clusters into a single desktop workstation. 748GB of unified memory means developers can run models with hundreds of billions or even trillions of parameters locally, without cloud dependency.

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② Intel Crescent Island: Inference-Specialized AI GPU​

At Computex, Intel disclosed detailed specifications for its next-generation datacenter AI inference GPU, Crescent Island.

Item	Specification
Memory	Up to 480 GB LPDDR5x
Power	350 W (PCIe form factor)
Precision Support	FP4/MXFP4 → FP64 (full precision coverage)
Target	AI inference workloads (Agentic Inference)
Positioning	Better price-performance than HBM solutions
Shipping	H2 2026

Significance: Crescent Island represents Intel's key strategic move in the AI inference market. 480GB of massive LPDDR5x memory (non-HBM) means significantly lower cost compared to NVIDIA H200/B200 and other competing products, targeting enterprise inference deployment scenarios.

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③ Intel Xeon 6+ (Clearwater Forest): First Intel 18A Datacenter CPU​

Intel also unveiled the new Xeon 6+ processor, codenamed Clearwater Forest, its first datacenter CPU built on the 18A process:

• 288 Darkmont architecture cores
• L2 288MB + L3 576MB cache
• 12-channel DDR5-8000 memory
• Foveros Direct 3D advanced packaging
• AI Agent Era: CPU returns to the center of infrastructure

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④ NVIDIA RTX Spark Ecosystem Takes Shape​

This week, the RTX Spark super chip developed in collaboration between NVIDIA and MediaTek continued to generate buzz. Multiple OEMs showcased RTX Spark-based laptop and compact desktop prototypes:

• ASUS, Dell, HP, Lenovo, Microsoft Surface, MSI all confirmed as launch partners
• Equipped with 20-core Grace CPU + Blackwell GPU (6144 CUDA cores)
• AI compute 1 PFLOPS
• Retail availability Fall 2026

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⑤ Intel × Foxconn AI Infrastructure Partnership​

Intel and Foxconn announced a joint AI infrastructure initiative, covering the complete chain from chip → server → rack-scale system, targeting the datacenter market opportunity driven by surging AI inference demand.

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⑥ Domestic AI Chip Developments​

According to the IDC 2025 annual report, total AI accelerator card shipments in China reached approximately 4 million units, with domestic vendors shipping approximately 1.65 million units, capturing a market share exceeding 41%. Huawei's Ascend 950 series has entered mass production and delivery, while Cambricon's MLU690 has begun shipping to internet customers.

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This Week's Compute Roundup​

Vendor	Product	Highlight	Timeline
NVIDIA	DGX Station for Windows	20 PFLOPS, 748GB unified memory	Q4 2026
NVIDIA	RTX Spark	1 PFLOPS AI PC chip	Fall 2026
Intel	Crescent Island GPU	480GB LPDDR5x, 350W	H2 2026
Intel	Xeon 6+ (Clearwater Forest)	288 cores, Intel 18A	H2 2026
Intel + Foxconn	AI infrastructure partnership	Chip→rack full chain	Strategic partnership
Huawei	Ascend 950PR/DT	1 PFLOPS FP8, self-developed HBM	In mass production
Cambricon	MLU690	2 PFLOPS FP8, 192GB HBM3E	Shipping

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Sources: NVIDIA GTC Taipei 2026 / Computex 2026 official announcements, Intel press releases, ifeng Tech, IT Home.

June 2026 — Huawei's Ascend 950 series (950PR / 950DT) has entered formal mass production and delivery, a landmark event for China's AI chip industry in 2026. Meanwhile, Cambricon's MLU690 has begun shipping and Moore Threads has announced MTT S5000 specifications, formally establishing China's tri-polar AI chip landscape.

Ascend 950 Series: A Historic Breakthrough with Self-Developed HBM​

Huawei HiSilicon's Ascend 950 series is the fourth-generation Ascend AI chip, first revealed at Huawei Connect 2025 in September and entering mass production in Q1 2026.

950PR (Prefill Inference Specialized)​

Item	Specification
Architecture	Da Vinci v5 (SIMD + SIMT dual-model)
Process	N+2 (SMIC domestic)
HBM	HiBL 1.0 (Huawei self-developed) , 128 GB
FP8 Compute	1 PFLOPS (HiF8 format)
TDP	~400 W
Target	Inference Prefill (video recommendation, real-time interaction)

950DT (Decode + Training Specialized)​

Item	Specification
Architecture	Da Vinci v5 (SIMD + SIMT dual-model)
Process	N+2 (SMIC domestic)
HBM	HiZQ 2.0 (Huawei self-developed) , 144 GB, 4 TB/s
FP8 Compute	1 PFLOPS (HiF8 format)
TDP	~500 W
Target	Inference Decode + Model Training

Historical Significance​

Self-developed HBM (HiBL 1.0 / HiZQ 2.0) represents the most important technical breakthrough of Huawei Ascend 950 — this is the first time a Chinese enterprise has achieved self-developed mass production of HBM memory, completely eliminating dependence on SK Hynix / Samsung HBM supply. Combined with the domestic N+2 process, Ascend 950 has achieved full-chain domestic production from HBM → Compute Die → Packaging → System.

Cambricon MLU690: China's Only Native FP8 Support​

Cambricon's seventh-generation AI chip MLU 690 (Siyuan 690) began volume production and shipping in H1 2026. This is the first domestic AI chip with native FP8 precision support.

Item	MLU 690
Process	5nm (TSMC / SMIC)
FP8 dense	2 PFLOPS
HBM	192GB HBM3E, 5 TB/s
TDP	~500 W
Unit Price (OAM)	~$8,000-12,000

MLU 690's FP8 compute power (2 PFLOPS dense) is on paper comparable to NVIDIA Blackwell (B200 FP8 4.5 PFLOPS sparse). Leveraging its financing advantage as a STAR Market listed company, Cambricon targets 2026 revenue of ¥15-20B (2025: ¥7.2B).

Moore Threads MTT S5000: From Graphics to Training-Inference Unified​

Moore Threads publicly disclosed detailed specifications of the MTT S5000 in February 2026, featuring the fourth-generation MUSA "Pinghu" architecture, single-card AI compute of 1,000 TFLOPS, 80GB GDDR6X memory, 1.6 TB/s bandwidth.

Moore Threads pursues a full-function GPU path (graphics rendering + AI compute + general-purpose compute), closest to NVIDIA's strategy. The founding team comes from former NVIDIA China, and the MUSIFY toolchain helps auto-migrate CUDA code to the MUSA platform, lowering ecosystem migration costs.

China's Tri-Polar AI Chip Landscape​

Dimension	Huawei Ascend	Cambricon	Moore Threads
Core Architecture	Da Vinci v5	MLUv07	MUSA 4th Gen
Process	N+2 domestic	5nm	6nm
FP8 Compute	~1 PFLOPS	2 PFLOPS	0.5 PFLOPS (estimated)
HBM Self-Sufficiency	✅ Self-developed HiBL/HiZQ	❌ Purchased	❌ Purchased
Ecosystem	CANN + MindSpore	NeuWare + MindSpore	MUSA + MUSIFY
Advantage	Full-chain domestic	Highest FP8 compute	Full-function + CUDA migration
2025 Revenue	(Huawei internal)	¥7.2B	¥2.2B

Global Market Comparison (Q2 2026 Update)​

Tier	Vendor	Flagship Chip	FP8/PFLOPS	HBM	Mass Production
Tier 1	NVIDIA	Rubin R200	25 PF (sparse)	288GB HBM4	2026 H2
Tier 2	AMD	MI400	20 PF (dense)	432GB HBM4	2026
	Huawei	Ascend 950DT	1 PF (dense)	144GB self-developed HBM	2026 Q1
	Cambricon	MLU690	2 PF (dense)	192GB HBM3E	2026 H1
	AWS	Trainium 3	5.7 PF (dense)	144GB HBM	2025 Q4 GA
Tier 3	Intel	Gaudi 3	1.8 PF	128GB HBM2e	In production
	Google	TPU v7	4.6 PF(TFLOPS)	192GB HBM	2025
	Moore Threads	MTT S5000	1 PF	80GB GDDR6X	2025 Q1

Note: NVIDIA uses sparse compute as standard, while AMD / Huawei / Cambricon use dense — not directly comparable.

Outlook for H2 2026​

• NVIDIA Rubin R200: Official shipment in H2 2026, 288GB HBM4, 6-chip CoWoS-L packaging
• Huawei Ascend 960: Roadmap H2 2027, expected FP8 compute doubled to 2 PFLOPS
• Cambricon MLU790: Expected 2027, 3nm, 384GB HBM4, 2.5 PFLOPS
• Moore Threads: Next-gen GPU expected with HBM3, 2× MTT S5000 compute

By 2026, China's AI chip industry has formed a complete product matrix from Training (Cambricon MLU690 / Ascend 950DT) → Inference (Ascend 950PR / Moore Threads S5000) → Systems (CloudMatrix / Distributed Clusters).

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This article is based on public information from Huawei Connect 2025 (2025-09-18), industry analysis reports from April 2026, and the latest market data as of June 2026.